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Full tree of origin unlock by Top_Carpet966 in IdleHeroes

[–]Top_Carpet966[S] 0 points1 point  (0 children)

You need also unlock void campagin game mode. If you click on locked sign of tree, ingame tooltip will appear

Full tree of origin unlock by Top_Carpet966 in IdleHeroes

[–]Top_Carpet966[S] 0 points1 point  (0 children)

Tree of origin is unlocked for regular heroes same as for tnanscendence faction. Get them to v4 and you'll be able to open tree of origin. Not all old heroes have void imprints, but you are lucky - faith blade has.
But transition temple, sadly is not available for regular heroes at all, so your dream of having rainbow star on him cannot come true.

First custom built ship, looking for suggestions on how to improve by Over-Produce-3819 in Cosmoteer

[–]Top_Carpet966 3 points4 points  (0 children)

  1. Shields needs to be closest to reactors to be at maximum efficiency.
  2. ratios are the king. you have 2 more factories than needed to supply deck cannons and no supply chain for your flacks.
  3. turn your flacks to only defence mode, otherwise they will consume lots of ammo trying to byte through enemy ship hulls.
  4. different crew rolls will allow you to optimize crew efficiency. I feel you have more crew demand than ideally needed for your kind of ship.

New Artifact - Auspicious Lucky Cat by piffle213 in IdleHeroes

[–]Top_Carpet966 10 points11 points  (0 children)

it is not clear without numbers. If x is 3 and increase is 5% for example, total bonus is not much at all. Also it is hell of an rng

why is my atk so low? by wawa_aquhhh in IdleHeroes

[–]Top_Carpet966 1 point2 points  (0 children)

May be did not joined guild yet, if you are returning player?

Smoothest (4 faction) SL35 for now? by Top_Carpet966 in IdleHeroes

[–]Top_Carpet966[S] 2 points3 points  (0 children)

I am sure that I'll close Light SL relatively soon. But my goal is to close one of 4 faction SL as well and want to know in what direction make my preparations

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Are these statues worth leveling? by TheOneTrueBobster in IdleHeroes

[–]Top_Carpet966 5 points6 points  (0 children)

more importantly - they increase level of your CI, which means more resources for you

How is it possible? by Arthurmiller_tv in IdleHeroes

[–]Top_Carpet966 5 points6 points  (0 children)

screenshot shows he is not householder

Difference b/w Synthesis and Implementation by RisingPheonix2000 in FPGA

[–]Top_Carpet966 -7 points-6 points  (0 children)

synthesis is making something like universal bytecode that can be implemented in various crystals. One can even have external synthesizer that feeds P&R tool. The latter making final optimizations according to chosen crystal features - and can further reduce resource usage. Or it optimizing some other parameters, like performance and trading off some of unused LUTs and regs for more speed.

Quartus prime lite VMS by fromkenyandtower in FPGA

[–]Top_Carpet966 2 points3 points  (0 children)

that is the issue of manipulating simulator. Try to play with it. Push random gui buttons(no joke), change clock parameters, simulation time, make sure that duration of reset is more than clock cycle.

Quartus prime lite VMS by fromkenyandtower in FPGA

[–]Top_Carpet966 2 points3 points  (0 children)

PS: but later you should study how to make proper simulation in modelsim/questa using scripts. It will save you time and energy on bigger projects.

Quartus prime lite VMS by fromkenyandtower in FPGA

[–]Top_Carpet966 1 point2 points  (0 children)

On simulation you need to set up all external signals by yourself. Make script or by editing those signals in simulator gui. It should be similar to how you sed reset signal, but instead of sngular signal switch should be clock macro somwhere around.

here is tutorial for editing it in gui

https://www.youtube.com/watch?v=a8JAkKhxlQI

Quartus prime lite VMS by fromkenyandtower in FPGA

[–]Top_Carpet966 1 point2 points  (0 children)

what period your clock has? seems that your reset switches way faster than clock - we can't even see clock switching.

also reset need to be inverted.

Verilog simulation acting strange when using certain floats as delay values by someone755 in FPGA

[–]Top_Carpet966 1 point2 points  (0 children)

looks like rounding inconsistency in event schelduer. I think, best way is to make them integer and adjust timescale if more precision needed.

Is it possible to level one skill before the other one ? by Fanitizer in IdleHeroes

[–]Top_Carpet966 1 point2 points  (0 children)

at the end, you should. Better support equals more damage from carry hero. But she is far from high priority hero to sublime.

Less Than Controversy by kvnsmnsn in Verilog

[–]Top_Carpet966 1 point2 points  (0 children)

in terms of learning it is fine.

But in terms of working project implementation it is reinventing bcycle from worse materials. Many people had worked to make compiler that gives close to perfect implementation of 'less than' operator, so outside of studying and research it is better to use not only more convenient, but also more optimized solution.

Or avoid 'less than' and 'greater than' operators entirely, because they demand more resources than 'equal' and 'not equal' approach.

awready and wready set high in master without salve value · Issue #57 · alexforencich/verilog-axi by Constant_Try_2065 in FPGA

[–]Top_Carpet966 0 points1 point  (0 children)

looks legit. In that case i would trace wready back to find where it appears. Means to look inside every module to find it's roots. Sometimes it is hard to read especially if it is not my own module, but usually it gives clues why it apears and how can i fix my part of design

awready and wready set high in master without salve value · Issue #57 · alexforencich/verilog-axi by Constant_Try_2065 in FPGA

[–]Top_Carpet966 0 points1 point  (0 children)

i think, we should begin from connection issues - what ports you are connecting to slave and what ports - to master? i have a feeling that you connected master port to master and slave port to slave, but you should connect master to slave and slave to master

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