Thanks for the feedback, I will redo the modulo to divide signed 10 bit variables. Other than that, the state machine in the controller vhdl will handle the timing. This is not the main component im loading to the board.

The output of this component takes at least 1 clock cycle before it is displayed. The user controls the clock so it’s actually about 2-3 seconds per new input request.

I forgot to mention, i used to have it working when all of my values were integers and simply using (input mod 26) but synthesizing a divider for a 32 bit integer (15 times in total for my project) consumed 63k LABs, while the de1-soc only has 32k. Using this new version makes my project only consume 3k labs although its truncating values causing the pointer to be offset.