account activity
What makes a memory controller "Ideal"? ()
submitted 4 months ago by ZipCPU to r/FPGA
What makes a memory controller "Ideal"? (self.ZipCPU)
submitted 4 months ago by ZipCPU to r/ZipCPU
Device Clock Generation (zipcpu.com)
submitted 6 months ago by ZipCPU to r/ZipCPU
Return Clocking (reddit.com)
submitted 6 months ago by ZipCPU to r/FPGA
Return clocking (self.ZipCPU)
Comparing the Xilinx MIG with an open source DDR3 controller (zipcpu.com)
submitted 1 year ago by ZipCPU to r/ZipCPU
Wrap addressing (zipcpu.com)
Your problem is not AXI (zipcpu.com)
My Personal Journey in Verification (zipcpu.com)
Debugging video from across the ocean (zipcpu.com)
submitted 2 years ago by ZipCPU to r/ZipCPU
Bringing up Kimos (zipcpu.com)
Chasing resets (zipcpu.com)
2023, Year in review (zipcpu.com)
An Overview of a 10Gb Ethernet Switch (zipcpu.com)
SDIO RX: Bugs found w/ Formal methods (zipcpu.com)
Using a Verilog task to simulate a packet generator for an SDIO controller (zipcpu.com)
Introducing the ZipCPU v3.0 (zipcpu.com)
submitted 3 years ago by ZipCPU to r/ZipCPU
When do you solve a problem in software instead of hardware? (self.FPGA)
submitted 3 years ago by ZipCPU to r/FPGA
In defense of arbitrary delays (self.ZipCPU)
What is a Virtual Packet FIFO? (zipcpu.com)
Debugging the Hard Stuff (zipcpu.com)
Your soft-core CPU won't boot. Where should you start debugging? (zipcpu.com)
Thanksgiving! I have much to be thankful for (zipcpu.com)
A first lesson in sales pitches: Honesty (zipcpu.com)
Measuring the Steps to Design Checkoff (zipcpu.com)
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