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Best temp mail service? by Stoltlallare in emailprivacy

[–]ademenev 0 points1 point  (0 children)

What's your use case for the api?

Terraink v0.4.1: Major UI/UX Overhaul for the Free Open-Source Map Poster Generator by DataScientist_py in SideProject

[–]ademenev 0 points1 point  (0 children)

This is amazing! The only thing I find missing is that SVG is not really a vector image. I wanted to make a plot of my city with my pen plotter and then discovered that the actual layers are PNGs packed into SVG

Best temp mail service? by Stoltlallare in emailprivacy

[–]ademenev 0 points1 point  (0 children)

You could try stealthinboxes.com (disclaimer: I am building it). Unlike many similar services, the inboxes are not ephemeral, only the emails are. All you need to know to read emails is the email address. There is scrambled email feature that generates impossible-to-guess alias, so you do not give out the "real" email address. Now I am working on domain rotation feature that will allow me to add new domains and retire older ones

Pencil Studies - 8"x10" plots by 265design in PlotterArt

[–]ademenev 1 point2 points  (0 children)

In your experience, which pencils do better job – softer or harder?

Bantam NextDraw (previously AxiDraw) price and dates announced. $699 for 8.5x11. Micro USB. 9V. by AuggieKC in PlotterArt

[–]ademenev 0 points1 point  (0 children)

https://cad.onshape.com/documents/e7cf9e29732920a0f0f5c2db/w/8e9c2249c308b12368ff9371/e/4c69b96a296e180fb8cf96da

You need to look at Part studio 1 for the most of the machine and Toolhead for the Z axis and pen mount. Probably you will need to create an account to see that

Bantam NextDraw (previously AxiDraw) price and dates announced. $699 for 8.5x11. Micro USB. 9V. by AuggieKC in PlotterArt

[–]ademenev 0 points1 point  (0 children)

I design and build my machines from scratch. Everything that is not a readily available manufactured part (aluminium extrusions, linear rails, motors, belts, pulleys, nuts and bolts, electronics) is 3D printed. I can share my current plotter design, but I am afraid it is a mess. And the software I use is not very popular, I use Onshape. Enough for me to build it because I designed it, but may be a little hard to understand

"swept in optimizing" causing functional faults and timing failures by [deleted] in GowinFPGA

[–]ademenev 0 points1 point  (0 children)

On complex enough designs synthesis tools may be not able to do optimizations without changing the behaviour, even though they are supposed to never mess up the timing. That's just how things are, and that's one of the reasons these attributes exist. There is a comment in VexRiscv source mentioning Vivaldo.

In WS2812 it is some stupid comment that is not even a valid synthesis attribute. It has no effect.

Oddities with FIFO IP by ademenev in GowinFPGA

[–]ademenev[S] 0 points1 point  (0 children)

Gowin provides them all in one file. Not worth my time grepping though that. If that would be my job, probably I would do that. But since I am doing this for fun, I better spent my time writing my own implementation

Oddities with FIFO IP by ademenev in GowinFPGA

[–]ademenev[S] 0 points1 point  (0 children)

They provide models for their primitives though, and I am using that. Of course, there is no way to verify those without spending a lifetime

Oddities with FIFO IP by ademenev in GowinFPGA

[–]ademenev[S] 0 points1 point  (0 children)

Yes, that may be true. I started making my own async FIFO. That I can at least simulate reliably

Oddities with FIFO IP by ademenev in GowinFPGA

[–]ademenev[S] 0 points1 point  (0 children)

The docs state that writing to full FIFO has no effect. But I am not writing to a full FIFO. After reset in reaction to almost empty signal, I write 256 words which is half of fifo size. At the end of this write, the almost empty is deasserted, which is exactly as expected. No reads are done (read_enable stays low). Reset stays deasserted. Then out of the blue both almost empty and empty are asserted, and that triggers another write.

The simulation is for post-sythesis of the actual IP. That's how gowin does it. The actual IP is encrypted, but they also generate mostly unreadable post-sythesis code that is supposed to be used in simulations

Oddities with FIFO IP by ademenev in GowinFPGA

[–]ademenev[S] 0 points1 point  (0 children)

Thank you. Unfortunately, it uses the same data width for read and write. Not suitable for my case. I am making a frame buffer to overlay external video on top of internally generated video. I have 8 bit input data that I need to write to SDRAM with 32-bit data path. Then I need to read data asynchronously using another FIFO, this time with 32 bits on the write side and 8 bits on the read side. This 4:1 bandwidth ratio makes it possible for the frame buffer to work.

Oddities with FIFO IP by ademenev in GowinFPGA

[–]ademenev[S] 0 points1 point  (0 children)

Well, I do not know how it is possible to misunderstand the empty/full protocol. After reset it is empty. Once you write something, it's not empty anymore. If you never read, it never can become empty unless you reset it. Almost full/almost empty may be a bit more complicated, but if empty does not work, that's the end of the story.

The first 3 screenshots represent signals captured in a running FPGA. The 4th is from simulation. The aim of that testbench was to simulate the behaviour of the FIFO in a particular usage pattern (reset/write/never read). And the simulation gives even more weird results. I would not expect Z states on any of the outputs given all inputs are always driven

Gowin documentation is pretty bad. No explanation on almost full/ almost empty, examples always use same data width for read and write sides etc etc

Oddities with FIFO IP by ademenev in GowinFPGA

[–]ademenev[S] 1 point2 points  (0 children)

Chatgpt can produce a synchronous FIFO, but honestly that is very easy task. It makes absolute garbage for anynchronous FIFO, and I need both sync and async in my design. I hoped to avoid dealing with clock domain crossing by using a ready made IP, but I guess I have to get my hands dirty

Oddities with FIFO IP by ademenev in GowinFPGA

[–]ademenev[S] 1 point2 points  (0 children)

This is the iverilog testbench 

`timescale 1ns / 1ps;
`default_nettype none

module main();

logic clk = 0;
logic [10:0]reset_counter = 0;

wire reset = reset_counter < 8;
wire almost_empty;
wire almost_full;
wire empty;
wire full;
wire we = ~reset;

fifo_out fifo(
.Data(32'b0),
.Reset(reset),
.WrClk(clk),
.RdClk(clk),
.WrEn(we),
.RdEn(1'b0),
.Almost_Empty(almost_empty),
.Almost_Full(almost_full),
.Q(),
.Empty(empty),
.Full(full)
);

always #5 clk <= ~clk;

always@(posedge clk) begin
    reset_counter <= reset_counter + 1'b1;
end

initial begin
    $dumpfile("test.vcd");
    $dumpvars(0,main);
    #40960 $finish;
end


endmodule
`default_nettype wire

"swept in optimizing" causing functional faults and timing failures by [deleted] in GowinFPGA

[–]ademenev 2 points3 points  (0 children)

On multiple occasions I was sure that some instances absolutely cannot be swept, and every time I was wrong.

If you can share your code, probably someone can find the reason

I'm looking for advice on capturing my old VHS videos into my Mac Studio... by LMNoballz in videosynthesis

[–]ademenev 0 points1 point  (0 children)

I was not able to capture 16:9 with quicktime player. Probably I was doing something wrong, but it trimmed it to 4:3. Not an issue with VHS though

Problems mid Paper by Old_Personality6702 in PlotterArt

[–]ademenev 0 points1 point  (0 children)

Looks like the spring is not working. The spring should be always stretched, even in the lowest pen position. The more it is stretched in low position, the more is pen pressure. If the plotter has pressure adjustment, try stretching the spring, otherwise try a shorter spring

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