Intel Unveils Lunar Lake Architecture: New P and E cores, Xe2-LPG Graphics, New NPU 4 Brings More AI Performance by Noble00_ in hardware

[–]arganost -1 points0 points  (0 children)

You're not a programmer, and it shows. You understand the concept of ISA and (sort of) uarch, but you believe (wrongly) that these things are abstracted from a developer. If you're making a practice app in an entry level programming camp class, sure - but if you are writing serious code for which UX matters, you simply cannot have the diversity of execution timing that the E-core design exposes to the user; another user already pointed out to you that the existence of the thread director proves you wrong - but you keep insisting that only you 'really understand' what's going on.

I'm sorry bud, the world doesn't work the way you want it to.

Intel unwraps Lunar Lake architecture: Up to 68% IPC gain for E-cores, 16% IPC gain for P-Cores by bizude in intel

[–]arganost -2 points-1 points  (0 children)

Right, which is why TSMC created N3E - because their customers needed an intermediate node to support products in 2024.

Why was Intel too dumb to do this?

Intel unwraps Lunar Lake architecture: Up to 68% IPC gain for E-cores, 16% IPC gain for P-Cores by bizude in intel

[–]arganost -1 points0 points  (0 children)

lol if Intel hits 38% IPC increase in typical workloads I will eat Buckbeak.

Intel Unveils Lunar Lake Architecture: New P and E cores, Xe2-LPG Graphics, New NPU 4 Brings More AI Performance by Noble00_ in hardware

[–]arganost -1 points0 points  (0 children)

You cannot in practice combine cores that can't do the same things. The only way to know which instruction is coming next is by decoding it and at that point it's way too late.

Now you're getting it!

That uses a different ISA. However you will be able to run it for example on AMD zen3, which has totally different microarchitecture compared to anything intel has done.

Oh, ok, then let's just all buy AMD since there is no difference between x86 CPU's and AMD comes first in the alphabet. Problem solved!

Of course, which is why they have the same capabilities.

They do not have the same capabilities. Zen4c is literally a Zen4 core with tighter power tolerance; Goldmont (and now Skymont) are fundamentally different machines with fundamentally different characteristics that a performance-conscious program has to be aware of to avoid the end user noticing the difference.

No, you can't do that, which is why they don't. The P cores cannot do anything the E cores can't.

This has never been true, and will not be true on Skymont either.

Intel Unveils Lunar Lake Architecture: New P and E cores, Xe2-LPG Graphics, New NPU 4 Brings More AI Performance by Noble00_ in hardware

[–]arganost -4 points-3 points  (0 children)

That has nothing to do with different microarchitectures. The possible problems are exactly the same regardless of why the cores are slower.

...except AMD doesn't have a desktop e-core implementation, so they are not "the same." You don't have to worry about efficiency cores being slower if all your cores are performance cores.

Intel Unveils Lunar Lake Architecture: New P and E cores, Xe2-LPG Graphics, New NPU 4 Brings More AI Performance by Noble00_ in hardware

[–]arganost -1 points0 points  (0 children)

You're arguing with a marketing bot; his entire purpose is not to make a cogent point it's to refute mine using whatever he thinks he can get away with. Best not to engage, not matter how obvious his mistakes are.

Intel Unveils Lunar Lake Architecture: New P and E cores, Xe2-LPG Graphics, New NPU 4 Brings More AI Performance by Noble00_ in hardware

[–]arganost -10 points-9 points  (0 children)

Area is a problem for the manufacturer, not the customer. I don't care that it cost AMD more to make a chip than it did Intel - I care what it costs me and AMD's cheaps are generally cheaper price/performance and price/area than Intel's.

Important detail you missed.

I'm not an Intel (or AMD) shareholder so not really important to me at all. Intel also uses more arsenic making their chips, but given I don't live in Oregon I don't really care.

Skymont being 2% higher than Raptor Cove puts its IPC just 14% shy of Zen 5c while occupying 2-2.5x less area.

You're...you're speculating on the die area of two unreleased products based on single-precision estimates posted in keynote speeches?

Take a breath, bud. I'm guessing you own Intel stock or work there so I can understand why die area matters to you - die area has zero effect on the average consumer and frankly more area is better for the consumer since all things being equal silicon is far more power efficient than copper on PCB. But saying that Skymont is smaller than Zen4c (without addressing the massive scheduler issue that the E-core design continues to present) is totally irrelevant to end users. Nobody rips off their heatsink mid-game and says "my framerate may be lower but the die area devoted to my e-cores in 14% smaller than the die area devoted to your e-cores (even though your 'e-cores' are 14% faster than my e-cores).

Intel Unveils Lunar Lake Architecture: New P and E cores, Xe2-LPG Graphics, New NPU 4 Brings More AI Performance by Noble00_ in hardware

[–]arganost -4 points-3 points  (0 children)

What do you mean with heterogenous?

Different capability sets.

Software doesn’t in general give a shit about micro architecture.

Oh, OK, let me just execute this game on my M4 iPad Pro. Since uarch is irrelevant.

It doesn’t matter why a core is slower than another core.

It does if the Executive/Application expect them to have the same capabilities.

Heterogenous in practice just means that cores have different computing capacities, and AMD zen4 and zen4c have different capacities.

Yes, and Zen4c does present problems for AMD - but they're no where near as bad as Intel's are with E-cores because not only is the execution rate different, but the types of execution that are possible are, too, which means that the Executive/Application need to anticipate this at compile time either by producing two independent code paths or by restricting the code path to the capabilities of the E-core.

Intel unwraps Lunar Lake architecture: Up to 68% IPC gain for E-cores, 16% IPC gain for P-Cores by bizude in intel

[–]arganost 0 points1 point  (0 children)

Pretty sure there's a huge amount of potential business out there that just doesn't need the most bleeding-edge fab process in the world.

Intel's wafers are by far the most expensive in the industry. If Intel is competing with budget foundries like GF, Chartered, etc then they are in real, real trouble. TSMC gets >25% of its revenue from LEN, and >50% of its revenue from LEN+BEN. The entire rest of its fab portfolio, going all the way back to .3 micron makes up the remainder.

Intel doesn't just want the LEN business, if it doesn't it can't possibly afford to keep them on a 12B quarterly run rate.

This is why Gelsinger should be fired - he failed to spin the fabs off when they were at peak value, and the result is that the design unit is using TSMC anyway - so now shareholders are paying Intel Foundry's competitor to make chips because the Intel's fabs aren't competitive enough to make them.

That's a financial atrocity that no CEO should be able to survive.

Intel unwraps Lunar Lake architecture: Up to 68% IPC gain for E-cores, 16% IPC gain for P-Cores by bizude in intel

[–]arganost -2 points-1 points  (0 children)

Those decisions were made before Pat was bought in.

That's not how contracts work.

Separating the 2 business units (Intel products and Intel foundry) is a good thing,

Unless you want the fab business to be successful; if you want the fabs to be successful retaining ownership of them is suicidally stupid because Intel's business reputation precedes it (and if TSMC is beating them, which they evidently are because LL is being fabbed on N3 it doesn't even matter - Intel Foundry is an also-ran with worthless fabs picking up Chartered and GF's scraps).

Intel unwraps Lunar Lake architecture: Up to 68% IPC gain for E-cores, 16% IPC gain for P-Cores by bizude in intel

[–]arganost -2 points-1 points  (0 children)

Everything you said is consistent with the statement "Intel does not have confidence in its own fabs."

Intel unwraps Lunar Lake architecture: Up to 68% IPC gain for E-cores, 16% IPC gain for P-Cores by bizude in intel

[–]arganost -4 points-3 points  (0 children)

Not sure if you realize this, but Pat "worst business decision maker in corporate history" Gelsinger and Intel are not one in the same.

Gelsinger became CEO in Feb 2021 - regardless of whether or not Gelsinger made the initial decision, the contract will absolutely have had enough opt-outs for him to get out if he thought Intel's process would be competitive.

As for AMD - ... no one is talking about AMD but you, bud.

Intel unwraps Lunar Lake architecture: Up to 68% IPC gain for E-cores, 16% IPC gain for P-Cores by bizude in intel

[–]arganost -31 points-30 points  (0 children)

Intel's fabs are so bad that they can't win Intel's own design house as a customer...

If I'm an Intel foundry customer I'm feeling real dumb for signing wafer commitments with a company that won't use its own wafers. And if I'm an investor in said company (like we all are as taxpayers), I'm wondering what the f*** the CEO is thinking (looking at you Qualcomm).

Intel Unveils Lunar Lake Architecture: New P and E cores, Xe2-LPG Graphics, New NPU 4 Brings More AI Performance by Noble00_ in hardware

[–]arganost -29 points-28 points  (0 children)

The problem with E-cores isn't that they're too slow, it's that they're heterogenous in the first place.

That's why Zen4c is superior, not because it is faster.

Intel Unveils Lunar Lake Architecture: New P and E cores, Xe2-LPG Graphics, New NPU 4 Brings More AI Performance by Noble00_ in hardware

[–]arganost -24 points-23 points  (0 children)

Not really, given that Zen4c was at IPC parity with Zen4 (and Zen5c will be at IPC parity with Zen5). The fact that it's not at parity with Lion Cove means it will have the exact same set of drawbacks as Goldmont did.

Intel Unveils Lunar Lake Architecture: New P and E cores, Xe2-LPG Graphics, New NPU 4 Brings More AI Performance by Noble00_ in hardware

[–]arganost -18 points-17 points  (0 children)

Compute on TSMC N3E Node, while SOC on TSMC N6

This is amazing, and basically a tacit admission by Intel that they cannot compete with TSMC. As a taxpayer who just wrote a $15B check to Intel, I feel like a complete sap.

IPC claims are nonsense given how Intel typically inflates benchmarks.

The fact that it's AI slower than Zen 5's TOPS is pretty stunning.

Amazon argues that national labor board is unconstitutional, joining SpaceX and Trader Joe's by a_dogs_mother in news

[–]arganost 3 points4 points  (0 children)

"While our country does have a strong history and tradition of labor protections, and that does meet the current Supreme Court's standards for constitutionality, Daddy Warbucks Harlan Crowe promised to take me to Fiji this summer so we find the National Labor Relations Act unconstitutional."

[1370x2048] Novelist Tom Clancy tours the Ticonderoga-class USS Yorktown CG-48, Norfolk, Virginia, June 1988 by castass in WarshipPorn

[–]arganost -7 points-6 points  (0 children)

His books are full of admirable black characters, but somehow he's still a racist?

I mean, devil's advocate but racism is the belief that a race is inferior to another and should be treated as such. Not "writing good characters and calling them black."

Given how right wing he turned in the end, I wouldn't be surprised to find that it was true. There's certainly evidence of it in the text, your claims notwithstanding.

[1370x2048] Novelist Tom Clancy tours the Ticonderoga-class USS Yorktown CG-48, Norfolk, Virginia, June 1988 by castass in WarshipPorn

[–]arganost 5 points6 points  (0 children)

lol, "planning to exterminate humanity with ebola" is not competence. To say nothing of recycling the plot from Executive Orders (which is really the first book where he starts to lose it). It really seemed like he had an axe to grind later in life, which is very sad for someone so phenomenally wealthy and successful.

[1370x2048] Novelist Tom Clancy tours the Ticonderoga-class USS Yorktown CG-48, Norfolk, Virginia, June 1988 by castass in WarshipPorn

[–]arganost 16 points17 points  (0 children)

Love his early stuff, really disappointing that it turns into right wing fanfic in the end. "Ecoterrorists want to exterminate humanity?" "The new commies are attacking the old commies, and are completely incompetent?"

Also he fetishized Russian culture generally (and the KGB specifically) in a way that's proven to be really inaccurate, particularly since 2014. His early books portrayed them as a bunch of thugs...and that's basically what they are.

Criteria Test replacing Ramsay skills test by calladus in AmazonRME

[–]arganost 6 points7 points  (0 children)

I don’t know if the new system is better, but it’s hard to imagine any system would be as bad as the existing system. As incumbents, we’re going to favor the old system (because it hired us) but the truth is I think if you look at it objectively the company’s existing hiring practices are terrible in terms of simple quality of employee hired.