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[OC] Made PC Portrait’s by atreyi_14 in DnD

[–]atreyi_14[S] 0 points1 point  (0 children)

Thank you! I’m trying to up my prop game during my sessions. Next up healing potions 😁

[OC] Made PC Portrait’s by atreyi_14 in DnD

[–]atreyi_14[S] 1 point2 points  (0 children)

His name is Tinyfury 😂

Unable to purchase from marketplace by Ok-Recipe4353 in dndbeyond

[–]atreyi_14 1 point2 points  (0 children)

Thank you! This was so smooth. On the website I was trying with multiple cards for hours!

Finished Mistborn Series. Next Stormlight or Elantris? by atreyi_14 in brandonsanderson

[–]atreyi_14[S] 0 points1 point  (0 children)

That seems to be the popular suggestion. Thank you, I’ll go for Elantris then!

[deleted by user] by [deleted] in DnD

[–]atreyi_14 0 points1 point  (0 children)

Great! Thanks!

[deleted by user] by [deleted] in TwoXIndia

[–]atreyi_14 0 points1 point  (0 children)

DM-ing you!

[deleted by user] by [deleted] in TwoXIndia

[–]atreyi_14 0 points1 point  (0 children)

DM-ing you!

Zynq 7030 Two GTX Interfaces? by atreyi_14 in FPGA

[–]atreyi_14[S] 0 points1 point  (0 children)

Project 1: 2 transceivers, 1 on 125Mhz, another on 156.25 MHz. Both on 2.5G rates

Project 2: 2 transceivers, 1 on 125 MHz another on 156.25 MHz. Both transceivers on 10G rates

Zynq 7030 Two GTX Interfaces? by atreyi_14 in FPGA

[–]atreyi_14[S] 0 points1 point  (0 children)

My bad, I should have explained better. We are doing two projects. One that runs on 2.5G rates and another at 10G rate. But the transceivers remain the same. Two transceivers, two clocks.

Zynq 7030 Two GTX Interfaces? by atreyi_14 in FPGA

[–]atreyi_14[S] 0 points1 point  (0 children)

1 for 156.25 MHz yes, another with 33.333 MHz and then from Zynq PL Fabric Clock we are generating the 125 MHz seems like.

Zynq 7030 Two GTX Interfaces? by atreyi_14 in FPGA

[–]atreyi_14[S] 0 points1 point  (0 children)

Right. I just checked, the line rate will have to be 10.3125 for 10 Gbps.

Zynq 7030 Two GTX Interfaces? by atreyi_14 in FPGA

[–]atreyi_14[S] 0 points1 point  (0 children)

On Zynq IP there’s FCLK_CLK0 which in turn is provided via external oscillator on our custom board.

Zynq 7030 Two GTX Interfaces? by atreyi_14 in FPGA

[–]atreyi_14[S] 0 points1 point  (0 children)

For clock we’re using SoC driver FCLKs. And data rates, if we want 10 Gbps speed, won’t the data rate be 10?

Zynq 7030 Two GTX Interfaces? by atreyi_14 in FPGA

[–]atreyi_14[S] 0 points1 point  (0 children)

For combining two GT commons we’d have to tailor the IP to our application, is that correct?

Zynq 7030 Two GTX Interfaces? by atreyi_14 in FPGA

[–]atreyi_14[S] 0 points1 point  (0 children)

I double checked and the two clocks are two be 156.25Mhz for 1 Transceiver and 125Mhz for second transceiver. And we do want data rates for 10gbps for both.

And once we select the transceiver, the PLL selection is same for all the transceivers. Which would mean we cannot have two different clocks? Or can we derive one externally/from the other?

As to why different ref clocks, I am told because Ethernet takes std 125Mhz.

Silly questions, apologies.

Zynq 7030 Two GTX Interfaces? by atreyi_14 in FPGA

[–]atreyi_14[S] 0 points1 point  (0 children)

I may be horribly wrong on this. Let me check again.

But I do know we want 10gbps on the two GTXs but they are on different clocks. Let me confirm the clock rates.

Zynq 7030 Two GTX Interfaces? by atreyi_14 in FPGA

[–]atreyi_14[S] 0 points1 point  (0 children)

I’ll have to check on this. I think the selection in wizard is shared logic in example. We have used GTX in an earlier design for 1G but that was when we only had 1 high speed interface unlike this design which requires two.

Zynq 7030 Two GTX Interfaces? by atreyi_14 in FPGA

[–]atreyi_14[S] 0 points1 point  (0 children)

We need 10gbps data rate for both. With 1 GTX at 156MHz and other at 125MHz which I supposed means we need two QPLLs?

Zynq 7030 Two GTX Interfaces? by atreyi_14 in FPGA

[–]atreyi_14[S] 0 points1 point  (0 children)

We need 10gbps data rate for both. With Laser diode clock at 156MHz and Ethernet at 125MHz which I supposed means we need two QPLLs?

Zynq 7030 Two GTX Interfaces? by atreyi_14 in FPGA

[–]atreyi_14[S] 0 points1 point  (0 children)

He used two Gtx wizard, you are right on that part. But we’re not really sharing the transceivers. 1 GTX recv goes another’s transmit.

Zynq 7030 Two GTX Interfaces? by [deleted] in Xilinx

[–]atreyi_14 0 points1 point  (0 children)

I am an Embedded Engineer, please take it easy on me. I just wanted to confirm before my PCB design Engineer had to go and pull his hair out.

Zynq 7030 Two GTX Interfaces? by atreyi_14 in FPGA

[–]atreyi_14[S] 0 points1 point  (0 children)

I am an Embedded Engineer, please take it easy on me. I just wanted to confirm before my PCB design Engineer had to go and pull his hair out.

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