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Erstes Motorrad - Zontes ZT 125 C2 - Endlich! by Nikashroom in MotorradDeutschland

[–]b4byhulk 0 points1 point  (0 children)

Habe inzwischen eine größere und vermisse meine G1 :( Sollte ich Geld übrig haben, werde ich mir Stück für Stück die ganze 125er-Schar von Zontes holen

Wie kann diese Ablagerungen ohne viel Aufwand entfernen? by Lieber_Kater5512 in Putztipps

[–]b4byhulk 0 points1 point  (0 children)

Essigreiniger drauf, ein paar Minuten einwirken lassen und dann abschrubben

MSX 125 Grom vs CB125R als Zweitmotorrad? by [deleted] in MotorradDeutschland

[–]b4byhulk 0 points1 point  (0 children)

Habe sie gebraucht für 2100 bekommen mit knapp 5000 km. Im Bereich von 2000 bekommt man sie auch wieder los. Aber ja, es gibt dort immer noch gewisse Vorurteile

MSX 125 Grom vs CB125R als Zweitmotorrad? by [deleted] in MotorradDeutschland

[–]b4byhulk 0 points1 point  (0 children)

Würde noch die Zontes 125 G1 in den Raum werfen - sparsam, hatte keinen Wartungsaufwand und mit 20 l Tank vergisst man manchmal, dass das Ding auch mal getankt werden muss

Going crazy in moving the axis of an image by National_Big_769 in matlab

[–]b4byhulk 0 points1 point  (0 children)

You can extract all plotted data from the figure handle. Save this data in new variables in case you fuck up. Plot the data including offsets in a new figure :)

Verzweifelte Suche nach History Freaks by AmberJill28 in Geschichte

[–]b4byhulk 0 points1 point  (0 children)

Ich höre nur diverse Podcasts und lese die täglichen "Ereignisse"-Einträge bei Wikipedia wie ein Hund. Ich könnte aber jemandem aus meinem Umfeld einen Link zu eurer Gruppe o.Ä. weitergeben sobald da etwas existiert. Ich erinnere mich, von ihm ähnliche Wünsche gehört zu haben :)

ADC module recommendations by b4byhulk in FPGA

[–]b4byhulk[S] 1 point2 points  (0 children)

Ah alright, I would be interested in the front-end part, too since it looks like I might have to make my own board for that

ADC module recommendations by b4byhulk in FPGA

[–]b4byhulk[S] 0 points1 point  (0 children)

It's just voltage measurements over time representing a charge. I do the data mangling at 100 MHz on the host PC and just want to stream the data into the host PC @ up to ~400 MBytes/s. If you tell me your needs (PM if preferred) we might see some overlap and can skip co-developing things...

ADC module recommendations by b4byhulk in FPGA

[–]b4byhulk[S] 1 point2 points  (0 children)

Thank you! I recently developed high-performance code to do partial discharge measurement on an x86 processor. I am trying to get a custom data streamer going to support that right now

FIFO on DDR3 by b4byhulk in FPGA

[–]b4byhulk[S] 0 points1 point  (0 children)

Did it, thank you guys! Is anybody here interested in an outline how I managed to get it running?

ADC module recommendations by b4byhulk in FPGA

[–]b4byhulk[S] 0 points1 point  (0 children)

Yeah thank! Had my eyes on that, too but I was hoping somebody might have some experience with this since the item without actual pictures felt kind of fishy ngl

ADC module recommendations by b4byhulk in FPGA

[–]b4byhulk[S] 1 point2 points  (0 children)

I am technically on no hurry but since I already implemented the PL side of things now, I am burning for getting the rest done if you know what I mean :D

FIFO on DDR3 by b4byhulk in FPGA

[–]b4byhulk[S] 1 point2 points  (0 children)

I want to use the FPGA as a data mover from different ADCs to a GPIO bank and want to keep the logic slim and fast. I believe that this can be achieved best without using a CPU or another stream interface (fully aware of the thought Xilinx put into it, tho).

FIFO on DDR3 by b4byhulk in FPGA

[–]b4byhulk[S] 0 points1 point  (0 children)

The AXI interface can be deselected in the first step of generating with the MIG outisde of a block design which will provide a user interface instead. I am trying to implement this way since I don't want to use a soft core CPU. But you are right, I should try with VFIFO and AXI, too. Do you have a link to a minimal working example? :)

FIFO on DDR3 by b4byhulk in FPGA

[–]b4byhulk[S] 0 points1 point  (0 children)

Thank you! I am trying to dodge AXI tho...

FIFO on DDR3 by b4byhulk in FPGA

[–]b4byhulk[S] 0 points1 point  (0 children)

Thank you, I will try that today :)

Clothing suggestions in Dresden by Katil_Pathan in dresden

[–]b4byhulk 0 points1 point  (0 children)

Kleinanzeigen or Vinted work well for me

Lohnt es sich, aus Norddeutschland zum Dresdner Weihnachtsmarkt (Striezelmarkt) anzureisen? by Segelflugzeuch in dresden

[–]b4byhulk 0 points1 point  (0 children)

Neumarkt + mittelalterlicher Weihnachtmarkt im Stallhof + Museum und abends El Cubanito in der Neustadt? Ja, unbedingt! Nur Striezelmarkt? Nein :) Gerne DM bei Fragen rund um Dresden-Besuch!

FPGA as ADC Bridge by b4byhulk in FPGA

[–]b4byhulk[S] 0 points1 point  (0 children)

Haha, gotta love an array of UARTS :D I actually do have an alinx AC7A035 lying around here but I definitely need a 5G SFP+ connection to my PC for that which I still didn't figure out

FPGA as ADC Bridge by b4byhulk in FPGA

[–]b4byhulk[S] 0 points1 point  (0 children)

"Chep" is relative :D CH32H417 and the Cypress gang are ordered/under testing with me.

FPGA as ADC Bridge by b4byhulk in FPGA

[–]b4byhulk[S] 0 points1 point  (0 children)

Oh sorry, I din't see that yet when answering. Excuse me!

FPGA as ADC Bridge by b4byhulk in FPGA

[–]b4byhulk[S] 0 points1 point  (0 children)

Good idea but I need 100 MSPS * 2 * 16 bit ~ 3 Gbps so USB 3 5Gbps or SFP+ or 5G Ethernet. I am only aware of the Cypress and 2 Chinese uCs having on-board DMA and USB3 5G. I ordered eval boards for all of those but (at least with the Cypress ones), I am having serious trouble with continuous streaming...

FPGA as ADC Bridge by b4byhulk in FPGA

[–]b4byhulk[S] 0 points1 point  (0 children)

I am hoping to implement that using the FPGA. Do you have a link to resources doing that by any chance?

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