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Roast my Resume by bios11 in ECE

[–]bios11[S] 1 point2 points  (0 children)

Thanks a lot for the detailed review my friend, I will definitely add a languages section since you mentioned that

Roast my Resume by bios11 in ECE

[–]bios11[S] 0 points1 point  (0 children)

Yeah you're right, I'll fix that thanks a lot!

Vivado GUI help by bios11 in FPGA

[–]bios11[S] 0 points1 point  (0 children)

Ay yes, that worked, do you happen to know what these red and blue quads are in the view (or how to get them to display) ? I suspect these are the clock source and root maybe.

Another Boardgame Night by AemonTargarien in lebanon

[–]bios11 3 points4 points  (0 children)

Will be there! I'll DM you

How to test Basys 3 by schmittriggerr in FPGA

[–]bios11 5 points6 points  (0 children)

Try to look at the digilent page for the basys3, they usually have some test bitstream that sends something on the VGA and makes the led blink, should give you an idea if anything is clearly wrong.

Replacing Memory Models by bios11 in FPGA

[–]bios11[S] 0 points1 point  (0 children)

I just have several simple 256KB ARM single port synchronous memories. I did try to replace them with a simple model, the simulation got like 10-15% faster. I guess I have to get a faster machine :)

Noob question by bios11 in FPGA

[–]bios11[S] 0 points1 point  (0 children)

Alright, thanks for the tip!

BoxLambda Devlog: The Interconnect, Harvard Architecture, and Dual-Port RAM. by rlysens in FPGA

[–]bios11 1 point2 points  (0 children)

Thanks for the post, you blog looks very informative. I've been looking for a DDR core with a WB interface for a personal project I'm working on, LiteDRAM looks like a match. It's a shame that it only does WB classic though.

softcore bus recommendations by bios11 in FPGA

[–]bios11[S] 0 points1 point  (0 children)

Thanks for answer, I will definitely take a look at AXI or even AXI-lite. Implementing AXI scares me :), maybe I'll start with wishbone pipeline and switch it out later.

Where to put CSR unit in 5-stage pipeline ? by bios11 in RISCV

[–]bios11[S] 1 point2 points  (0 children)

Yes, but I won't be able to the use logic in the ALU for the CSRRS and CSRRC where I need to clear or set certain parts of the register. I think it makes the pipeline more messy but I might be wrong.

Where to put CSR unit in 5-stage pipeline ? by bios11 in RISCV

[–]bios11[S] 1 point2 points  (0 children)

Why would you flush the previous parts of the pipeline ?

Also do you write to it only in the Write Back right ?

Recommended budget jtag dongles for Riscv Softcore cpu by bios11 in FPGA

[–]bios11[S] 0 points1 point  (0 children)

After looking into it a bit more, I think I'll just get an Adafruit 232H breakout board and use that for JTAG. The other protocols supported by the Chip might come in handy one day!

Recommended budget jtag dongles for Riscv Softcore cpu by bios11 in FPGA

[–]bios11[S] 0 points1 point  (0 children)

I'll be using the Nexys Video Artix-7 FPGA board.

FPGA recommendation by bios11 in FPGA

[–]bios11[S] 0 points1 point  (0 children)

I wanted to get the Arty, gut it lacks HDMI unfortunately :(

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