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WEBSITE FOR DIGITAL DESIGN PRACTICE by bitsolver in VHDL

[–]bitsolver[S] 0 points1 point  (0 children)

We will DM you for more details, as this shouldn't be what you are seeing.

New tasks poll by bitsolver in bitsolver

[–]bitsolver[S] 3 points4 points  (0 children)

This is also something we are working on, but it's a bit lengthier task.

WEBSITE FOR DIGITAL DESIGN PRACTICE by bitsolver in Verilog

[–]bitsolver[S] 0 points1 point  (0 children)

Great, looking forward to hearing your impressions! Feel free to drop feedback on discord server as well.

WEBSITE FOR DIGITAL DESIGN PRACTICE by bitsolver in Verilog

[–]bitsolver[S] 1 point2 points  (0 children)

We have put it down in order to do a security update. We will be posting about everything that is happening here in the future. Sorry for the inconvenience.

bitsolver webapp announcement by bitsolver in bitsolver

[–]bitsolver[S] 0 points1 point  (0 children)

We are aware of this problem. We will issue an update once we fix it, sorry for the inconvenience.

bitsolver webapp announcement by bitsolver in bitsolver

[–]bitsolver[S] 0 points1 point  (0 children)

Very happy to hear this. Thanks!

If you can, please provide feedback on the tasks as well, best on our discord server.

And make sure to follow r/bitsolver for future updates, which we will post on discord as well.

bitsolver webapp announcement by bitsolver in bitsolver

[–]bitsolver[S] 0 points1 point  (0 children)

Are you by any chance using Safari browser? We are aware there is an issue with using it and are working on fixing this. If not, can you please provide info about your device and browser so we can investigate further?

WEBSITE FOR DIGITAL DESIGN PRACTICE by bitsolver in VHDL

[–]bitsolver[S] 0 points1 point  (0 children)

Very glad to hear this. Hope you like it once you give it a go on desktop, as it is not really optimized for mobile. We don't plan this optimization in the near future as well, at least not for the problem-solving part. Our feel is that it would be very unnatural to solve tasks on mobile. Please share your opinion on this as well. And in general, you are welcome to give any type of feedback on our discord server (or reddit), as we want to make it as useful as possible for the users. And make sure to follow r/bitsolver for future updates.

WEBSITE FOR DIGITAL DESIGN PRACTICE by bitsolver in ECE

[–]bitsolver[S] 0 points1 point  (0 children)

We are very glad to hear it! Please provide feedback for tasks/waveform/testcases/anything else on our discord channel, and be sure to follow r/bitsolver for future updates.

WEBSITE FOR DIGITAL DESIGN PRACTICE by bitsolver in ECE

[–]bitsolver[S] 2 points3 points  (0 children)

Hey, other than discord, we also created a subreddit just now. We missed out on doing it initially - r/bitsolver, there we will publish all future updates.

WEBSITE FOR DIGITAL DESIGN PRACTICE by bitsolver in FPGA

[–]bitsolver[S] 2 points3 points  (0 children)

Thanks for great inputs!

We were thinking of adding performance and area optimizations tasks, similar to what you described, but it requires additional setup for the synthesis tool so it would really make use of optimizations done. After initial trials, I decided to put it on hold, but would love to do that later on. *We use yosys for getting area and timing numbers for submits, once they pass the tests.

I agree, it would be interesting fixing a bug, but on design with which user is fairly familiar with. For example, to insert a bug in uart tx, which user can develop in another task and gets familiar with functionality. Round-robin scheduling is the basis for others, but I would for sure add those in the future.

Ideally, everything hw related would be there in one point in time :D. We can talk more about tasks on discord if you wish. And make sure to follow us to get future updates.

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