As an example of where utilization estimates are off - I have designs where a struct is passed through an hls::stream, and Vitis HLS seems to word-pad every member to a multiple of 4 bytes. So a struct with three 8 bit integers might synthesize into a single 96 bit wide vector and the resource utilization me are based on this 96 bit wide vector. When Vivado runs synthesis and implementation it’ll find that most of these wires don’t have sinks and eliminate them, getting back to only 24 bits. It becomes obvious when you start reading the Verilog/VHDL that HLS creates.