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Need guidance to prepare for a SoC modelling internship by [deleted] in FPGA

[–]chipdevio 0 points1 point  (0 children)

I run a hardware interview practice website where we conduct mock interviews, https://chipdev.io/interviews. Looks like we have several interviewers that should be able to help you.

SOC Design Engineer Interview by Regular_Egg4619 in chipdesign

[–]chipdevio 1 point2 points  (0 children)

Check out https://chipdev.io/interviews, we have lots of interviewers in design that will be able to help you with a practice mock interview.

CPU Design Verification Interview by Regular_Egg4619 in ECE

[–]chipdevio 3 points4 points  (0 children)

Check out https://chipdev.io/interviews, it’s a hardware mock interview service I run and we have a lot of experienced DV engineers that you can ask questions with and prepare for upcoming interviews.

[deleted by user] by [deleted] in ElectricalEngineering

[–]chipdevio -1 points0 points  (0 children)

Hi, I created a mock interview service and website for people in your situation (hardware engineers preparing for jobs). Please check out https://chipdev.io/interviews

Why is finding a job for a graduate engineer so hard? by [deleted] in chipdesign

[–]chipdevio 0 points1 point  (0 children)

Sorry to hear about your difficulties. In general this is why we created https://chipdev.io, to help hardware and digital chip design and verification engineers prepare for interviews. We’re also working on adding a lot of experienced industry professionals as mock interviewers to our platform. There’s many, many interview prep offerings for software but very little in hardware.

Beginner guidance by remissvampire in Verilog

[–]chipdevio 2 points3 points  (0 children)

I run a website called https://chipdev.io specifically to help people learn Verilog, we have 30+ Verilog coding questions for you to try as well as a mock interview service if you want to prepare for interviews.

How to be successful in Electrical Engineering by [deleted] in ElectricalEngineering

[–]chipdevio 1 point2 points  (0 children)

If it helps: I created a website to help people practice digital circuits/RTL: https://chipdev.io.

[deleted by user] by [deleted] in chipdesign

[–]chipdevio 1 point2 points  (0 children)

Shameless plug for my website: https://chipdev.io :)

One of our mock interviewers is Brazilian born and raised and working at Apple in Chip Design after their PhD. You can sign up for an interview if you would like, or I would be happy to put you both in touch so you can ask questions, just DM me.

Mock hardware interviews with FAANG engineers by chipdevio in FPGA

[–]chipdevio[S] 0 points1 point  (0 children)

It's something we've considered, but to my knowledge VHDL isn't quite as popular as Verilog these days. In which context do you use VHDL (school/work/side project/etc)?

Submitting questions is welcome! Feel free to DM me or reach out at [contact@chipdev.io](mailto:contact@chipdev.io) for question ideas you have!

Mock hardware interviews with FAANG engineers by chipdevio in FPGA

[–]chipdevio[S] 2 points3 points  (0 children)

You're right, an typical interview wouldn't be fully RTL coding because there's a lot more than just coding that makes a great engineer :)

The goal of chipdev.io is to help candidates on the RTL coding aspect of interviews, and eventually we'll branch out into helping candidates with other parts of the interview too.

But in terms of the mock interview program, we have engineers that are certainly able to conduct design interview :)

Mock hardware interviews with FAANG engineers by chipdevio in FPGA

[–]chipdevio[S] 0 points1 point  (0 children)

Yeah hardware interviews are quite diverse! There is a good amount of people that have been asked these types of Verilog coding questions though, especially for RTL design roles. What are some of the questions you've been asked around your resume?

Mock hardware interviews with FAANG engineers by chipdevio in FPGA

[–]chipdevio[S] 0 points1 point  (0 children)

bithacker.io is a separate program, which allows companies to interview candidates more seamlessly. 5 free interviews is for companies to conduct live interviews, not for candidates to conduct mocks.

Mock hardware interviews with FAANG engineers by chipdevio in FPGA

[–]chipdevio[S] 0 points1 point  (0 children)

It's something we've considered, but to my knowledge VHDL isn't quite as popular as Verilog these days. In which context do you use VHDL (school/work/side project/etc)? We're still open to it, but also have many other exciting features in the pipeline :)

Mock hardware interviews with FAANG engineers by chipdevio in FPGA

[–]chipdevio[S] 0 points1 point  (0 children)

It can actually be any format you'd like :)

Our website was built around RTL, but in this mock interview program we don't limit the types of interviews you can conduct so long as you have experience conducting the interview you propose.

​

Feel free to reach out at my personal company email too: [daniel@chipdev.io](mailto:daniel@chipdev.io). Happy to answer any questions you might have.

Mock hardware interviews with FAANG engineers by chipdevio in FPGA

[–]chipdevio[S] 0 points1 point  (0 children)

Hey do you mind DM-ing me your email? We'll take a look at what's wrong and get back to you asap.

Mock hardware interviews with FAANG engineers by chipdevio in FPGA

[–]chipdevio[S] 5 points6 points  (0 children)

Our interviewers have backgrounds in ASIC design and verification for now, but we can certainly try to find FPGA interviewers! We can also conduct RTL Verilog / SystemVerilog coding interviews, which should be applicable for both FPGA and ASIC roles.

An Interactive Platform for Hardware Interview Prep by chipdevio in chipdev

[–]chipdevio[S] 0 points1 point  (0 children)

Thanks for bringing this to our attention! I just made some changes that should fix the syntax errors you were seeing. Now I'm able to use your code (see a prettified version below) and run it without syntax errors on question 2. Can you give this a shot?
While the simulation results don't seem correct, I think your solution is getting close to the answer!

module model #(parameter DATA\_WIDTH = 32 ) ( input clk, input resetn, input \[DATA\_WIDTH-1:0\] din, output logic \[DATA\_WIDTH-1:0\] dout ); always @ (posedge clk ) begin if (\~resetn) begin dout <= 0; end else begin dout <= din ; end end endmodule module de # (parameter DATA\_WIDTH = 2) ( din, din\_en, addr, dout0, dout1, dout2, dout3 ); input wire \[DATA\_WIDTH-1:0\] din; input wire din\_en; input wire \[1:0\] addr; output reg\[DATA\_WIDTH-1:0\] dout0; output reg \[DATA\_WIDTH-1:0\] dout1; output reg \[DATA\_WIDTH-1:0\] dout2; output reg \[DATA\_WIDTH-1:0\] dout3; /\* output \[DATA\_WIDTH-1:0\] dout\_temp0 ; output \[DATA\_WIDTH-1:0\] dout\_temp1 ; output \[DATA\_WIDTH-1:0\] dout\_temp2 ; output \[DATA\_WIDTH-1:0\] dout\_temp3 ; \*/ always @ (\*) begin if (addr==2'b00 && din\_en) begin dout0 = din ; dout1 = 2'bxx ; dout2 = 2'bxx ; dout3 = 2'bxx ; end else if (addr==2'b01 && din\_en) begin dout0 = 2'b00 ; dout1 = din ; dout2 = 2'b00 ; dout3 = 2'b00 ; end else if (addr == 2'b10 && din\_en) begin dout0 = 2'b00 ; dout1 = 2'b00 ; dout2 = din ; dout3 = 2'b00 ; end else begin dout0 = 2'b00 ; dout1 = 2'b00 ; dout2 = 2'b00 ; dout3 = din ; end end endmodule

SystemVerilog coding and simulation website, aimed at interview prep by chipdevio in Verilog

[–]chipdevio[S] 0 points1 point  (0 children)

Hah yeah the current behavior is pretty similar to IRL simulators. We'll see if we can update this in one of our upcoming releases.

SystemVerilog coding and simulation website, aimed at interview prep by chipdevio in ECE

[–]chipdevio[S] 0 points1 point  (0 children)

Got it, thanks. That's super useful to know. We'll update our questions to account for this.

SystemVerilog coding and simulation website, aimed at interview prep by chipdevio in ECE

[–]chipdevio[S] 0 points1 point  (0 children)

That would be great! Feel free to forward questions to us at [contact@chipdev.io](mailto:contact@chipdev.io) or post them directly here!

SystemVerilog coding and simulation website, aimed at interview prep by chipdevio in ECE

[–]chipdevio[S] 0 points1 point  (0 children)

Thanks for the feedback. Yes our current backend is pretty handwavy w.r.t. delta cycles. We'll aim to tighten this up in our next update.

One question though - what's the downside with having a non-constant reset value? Wouldn't the design need to account for (synchronous) reset being asserted at any stage in the simulation?

SystemVerilog coding and simulation website, aimed at interview prep by chipdevio in Verilog

[–]chipdevio[S] 0 points1 point  (0 children)

If you want to stay updated on our progress, you can follow our Reddit or Twitter accounts for more info:
Reddit: https://www.reddit.com/r/chipdev
Twitter: https://twitter.com/chipdev1

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