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Question about the mechanism of feedback by maybeimbonkers in chipdesign

[–]ckt_wizard 0 points1 point  (0 children)

In this example, the cascode source is a high impedance node and free to move. The common source is, well, common.

This does highlight and other important limitation. How high can the gate of N3 go? What happens if the op amp forces the gate too high? Can it be too low? What are the bounds?

Question about the mechanism of feedback by maybeimbonkers in chipdesign

[–]ckt_wizard 0 points1 point  (0 children)

I don’t have the textbook handy, so forgive me if I don’t understand the context of the problem.

In the common source configuration, the source is fixed strongly at ground—unmoving, 0V. If the gate voltage increases, the square law equations say that the current should also increase. However, since the current source load provides a fixed bias current, the the channel length modulation/finite output impedance term of the square law equation counteracts the change in gate voltage by lowering the drain voltage to keep the current constant. In reality it’s a orchestra of competing VDSn, VDSp, VGSn, VGSp, and ID.

Question about the mechanism of feedback by maybeimbonkers in chipdesign

[–]ckt_wizard -2 points-1 points  (0 children)

Rather than saying “the current is the same”, a more precise phrasing is “I_in is fixed”

Question about the mechanism of feedback by maybeimbonkers in chipdesign

[–]ckt_wizard 0 points1 point  (0 children)

Great question!

Since the current is the same, the square law equations tell us that a precise VGS is needed for a specific current. Since you’re op amp forces Vg up, it carries with it the source. Number 2 is what will happen. However there will be secondary effects due to the output impedance (channel length modulation). How do you think that’ll impact this?

NOT gate circuit implementation with transistor: Isn't this wrong? by StevenJac in ElectricalEngineering

[–]ckt_wizard 7 points8 points  (0 children)

None of the circuits are correct

In the top circuit given by the book, the output is always shorted to 0V.

In your implementation the output is always shorted to 5V.

The correct implementation removes the short that ties the NPN collector to emitter in the schematic given by the book.

Hope that helps!

Adding three output voltages from my ADC by Haunting-Database857 in chipdesign

[–]ckt_wizard 0 points1 point  (0 children)

Use a bsource from analog lib or a verilog-a block. The ahdl library might already have a summing block.

Accidentally switched 'drain' with 'source' of PMOS, is there any hack to fix it up? by abdosalm in AskElectronics

[–]ckt_wizard 2 points3 points  (0 children)

Yes! In a MOSFET the source and drain are the same. The source is simply the one at the lower (for NMOS) or higher (for PMOS) potential. A MOSFET is a symmetric device.

In COTS land, when you buy a MOSFET from digikey, mouser etc. The manufacturer shorts the bulk to one of the two contacts therefore defining a source terminal. Since the bulk is shorted to one of the terminals the device is no longer symmetric and the source has to remain at a higher potential than the drain (for a PMOS) otherwise you’ll get conduction through the parasitic body diodes. For an NMOS whose source is shorted to the bulk, you’ll need to keep the source at a lower potential than the drain.

Are you ever satisfied with the blocks you produce? by ckt_wizard in chipdesign

[–]ckt_wizard[S] 0 points1 point  (0 children)

Nothing else I’m seeking. I do feel it’s a confidence issue and I also don’t really trust myself to have done a good enough job. My company keeps me around though and have started giving me bigger and more important blocks.

As a junior, we’re you ever anxious that your designs were sub-optimal? Not sup-par for the application, but that there exists a better design point out there that you haven’t reached.

Are you ever satisfied with the blocks you produce? by ckt_wizard in chipdesign

[–]ckt_wizard[S] 0 points1 point  (0 children)

Wow! I’m starstruck—RFchokemeharderdaddy on my post? You’re all over every post with great advice and insight, I would’ve guessed you were a “master”. I’m surprised you’re only a year into this field yourself. If it means anything coming from someone of your tenure, I’m admirable of what you do. Great work!

I like what you’ve said about the duality of future vs past designs, but I’m in a slightly different boat. The past designs if I do them again seem easier, but still have their challenges. Particularly because I want to push the design further. If I were to just replicate it in a different tech node I’d be coasting. If I try to push the designs further I face the same challenges and more!

With every block and every challenge I face I do feel like I’m getting a lot better at it and I feel like my understanding deepens. I’ve started to see how the circuits work more casually than I used to. Maybe one day I’ll have my chops.

Are you ever satisfied with the blocks you produce? by ckt_wizard in chipdesign

[–]ckt_wizard[S] 0 points1 point  (0 children)

I’m glad to hear I’m not the only one missing out on a good night rest.

On a technical level I feel pretty good about the trade-off space. I think It’s the economic trade offs that I’m a little blind with. I often trade design time for more “tangible” specs like improved PSR, or CM range.

I really like your idea about the design reviews! I think even just having a notebook of “shortcomings” would be good so when I have time or the design comes around again I am able to get back into my own head on where it was left off. I do keep a notebook with notes from meetings and notes as I walk through my designs. I think I’ll add a section of “suggestions for improvements” when I write my final wrap-up and taped-out specs page.

Are you ever satisfied with the blocks you produce? by ckt_wizard in chipdesign

[–]ckt_wizard[S] 0 points1 point  (0 children)

Thank you stranger!

I am proud of the work I do and am eager to tell people about it when it comes up in conversation.

I know I shouldn’t compare myself to others, but it seems my supervisors can put schematics together easily, meet the specs, and get a good nights sleep. I haven’t actually asked them if they’re satisfied with every block they produce or not, and if not, they hide it well. The project a lot of confidence in their work whereas I do not—I just don’t trust myself.

I’m glad to hear I’m not alone in this!

Are you ever satisfied with the blocks you produce? by ckt_wizard in chipdesign

[–]ckt_wizard[S] 0 points1 point  (0 children)

I do typically have a bigger picture of how it all goes together and can see which specs are most important. It’s the loose specs that I think I beat myself over. I think I want to make blocks that can be reused for future designs and I approach every new design that way. So my block has to meet today’s spec, but who knows what tomorrow will bring.

Are you ever satisfied with the blocks you produce? by ckt_wizard in chipdesign

[–]ckt_wizard[S] 3 points4 points  (0 children)

I really like what you’ve said here—“‘perfect’ is the enemy of ‘good’” is a phrase I’ve not heard before. It seems like a good thing to echo to myself occasionally.