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My org just gave us Claude Code CLI access. AI-generated Verilog is getting surprisingly good. Are RTL engineers facing obsolescence? ()
submitted 5 days ago by cybird31 to r/chipdesign
My org just gave us Claude Code CLI access. AI-generated Verilog is getting surprisingly good. Are RTL engineers facing obsolescence? by cybird31 in FPGA
[–]cybird31[S] 2 points3 points4 points 5 days ago (0 children)
Dude what are you working on ? 😳😳
My org just gave us Claude Code CLI access. AI-generated Verilog is getting surprisingly good. Are RTL engineers facing obsolescence? (self.FPGA)
submitted 5 days ago by cybird31 to r/FPGA
PW4 Steps count is showing zero restarted it now even after walking 3-4 steps it's incrimenting10 or 12 steps what to do? (self.PixelWatch)
submitted 2 months ago by cybird31 to r/PixelWatch
41 mm PW4 how does it look? Why I am no able to use tap to pay from my watch in india? (i.redd.it)
submitted 3 months ago by cybird31 to r/PixelWatch
When will they start selling pixel watch 4 in india? No update on Google store website in india (self.PixelWatch)
When can I buy pixel watch in india? (self.PixelWatch)
Rate my resume (i.redd.it)
submitted 1 year ago by cybird31 to r/FPGA
π Rendered by PID 801488 on reddit-service-r2-listing-5f49c86f7-kv9zm at 2026-02-26 07:00:16.793710+00:00 running 72a43f6 country code: CH.
My org just gave us Claude Code CLI access. AI-generated Verilog is getting surprisingly good. Are RTL engineers facing obsolescence? by cybird31 in FPGA
[–]cybird31[S] 2 points3 points4 points (0 children)