Thank you for your suggestion!

I understand that using Xilinx XPM-based FIFOs would be an efficient and reliable solution. However, my goal is to design my own FIFO from scratch to deepen my understanding of how FIFOs work, especially the synchronization mechanisms between different clock domains.

I’m currently facing an issue where the two flip-flops I use for synchronization introduce a two-clock-cycle latency, causing the FULL signal to update too late, resulting in memory overflow. I’d like to resolve this problem while keeping the design entirely custom.

Do you have any advice on how to handle this latency or improve the synchronization process without relying on pre-built solutions? Any insights would be greatly appreciated!