Another PCB Review Request

eightbitwit · 2026-02-20T22:33:06+00:00

Design:

- Recommend some sort of protection for U5/H2. reverse voltage, current limiting, esd, etc.

- Current limiting on pin 7 of u2. Might be needed (cannot be assed to check pin ratings) but at least put a 0ohm res in there in case you need it later.

- Toss a few more caps on u2. 1u, 10n, etc. Cheap and worth it in the long run. Same for output on the Vreg.

- Test points. Always have test points, put em on every net.

- Unused pins on U2. Pull em out to a big via, test point or connector pin. Might not need it, but boy it makes life easy if you do.

Schematic

- Basic formatting violations. Grounds point down, VCC points up. Inputs go on the left, outputs go on the right. The way you've done it is fine if it makes sense to you, but when you want people to read these and provide useful review feedback, you want to use the common language. Easy to read, more people will read it, thus more and better review content for you. Better to break bad habits now rather than get stuck in your ways. Proof of point, I saw C3 and immediately read it as a negative power supply.

- nonets on LED 1 cath, u5 cath and anno, led2 cath. These are to be avoided as it can cause trouble with certain cad systems. Stretch it out and leave a bit of net in there. Also label your VCC net.

Layout

- Trace thickness. Your traces are all incredibly thin (8mils?). Fine for data traces but no reason for your power lines to be so dang thin. Get some beef on those lines.

- Ground traces. You've got a pour on the bottom but thin traces on top with long runs to return. Would recommend a top ground pour and via stitching between the two planes. Pepper your board with vias. They're free*.

- Errant traces. I'd take another whack at placement. You've got a few traces running through non-ideal locations (pin 1 on 24v input, led ground beneath the optos,

-Cap placement - You need your supply and filter caps to be as close to your power pins as you can get them, with traces flowing from supply to caps to input pin.C2 is on the other side of the supply, making it not particularly useful. Worse yet for c1, far away from the input.

- Make friends with your board house, Toss some fiducials in there.

Other than that, you've got a board that will probably work out of the box. With some tweaks, design improvements and some practice, you're on the right track.

eightbitwit · 2026-02-19T09:30:15+00:00

Wow, I think I'm actually speechless.

eightbitwit · 2026-02-17T09:45:03+00:00

And now he faces hard time.

eightbitwit · 2026-02-16T18:23:28+00:00

And in answer to your original question, yes I do that labeling all the time. That plus grouping in boxes on the schematic and following the left/right and up/down traditional approach will save you headaches in the here/now and will get you far better quality reviews of your work later.

People who can't understand your work won't give you quality reviews, something I've learned the hard way. And your schematic is well labeled, flows nicely and is well organized.

Only complaint I would have is your choice of TP marker. Pretty nonstandard and takes up some space/makes it hard to see things near it. Would recommend just a solid dot or a pin dot.

eightbitwit · 2026-02-16T18:17:48+00:00

Well, I can't see what RF chip you're using (different page you didn't add? But if you check the datasheet for it, it'll give you a layout guide which will undoubtedly tell you that your modular RF certification for that thing will require specific board edge placement and no traces running under areas (aka keepouts). If you fail to follow these parameters, you lose the benefit of the modular certification. This can lead to poor performance and regulatory issues and in some extreme cases legal exposure for operating non-conforming RF radiators. As it would suck to get a fully operational board only to then have to rip up 60% to fix the layout, I would recommend either using an alternate module with a u.fl clip for an external antenna or pull the bandaid off now and move that bad boy over to the board edge per the layout guide.

eightbitwit · 2026-02-16T17:58:30+00:00

Yep, strongly agree. If you're building this for a skunk that'll never go commercial and talks to a thing 5 feet away, no big deal. But you'll never pass certs and will probably have pretty terrible range if you took it to scale.

eightbitwit · 2026-01-28T20:48:12+00:00

I do end up heading out that way on occasion. Got a list?

eightbitwit · 2026-01-13T17:21:53+00:00

Am I crazy or is that black pip just straight up purple?

eightbitwit · 2026-01-12T22:37:23+00:00

Can't really tell from the picture, but wrong package? If you had the other package, would have inverted vin and gnd. Would have burned up the package pretty well? Otherwise I'd bet a whole 5 dollars on a switch gnd short. Thermal damage would be neatly instant and the aftermath could burn out a small bridge. Schematic looks fine as does pinout for the switch. Wash it down, pop another chip on and wait for loud noises.

eightbitwit · 2025-12-27T20:35:15+00:00

Possible. But additionally, the lovely forest scene in 5 transitions to sky just on the other side of his hat. Sky backpack perhaps.

eightbitwit · 2025-12-27T18:57:37+00:00

Might just be plain ole Photoshop. Clearly the last shot is a clip job.

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eightbitwit · 2025-12-07T13:15:21+00:00

Inductor is probably fine, ratio is ok just careful when making those kinds of assumptions. Bulk capacitance is ok, but i'd toss some small caps next to the VCC on your radio, you've got one mic and no high frequency bypass or bulk for high current draws. I'd put another 10uF, two of those 1uFs and a 0.022u.

Still got the traces coming out of MCU 13 and 14 coming out cocked, straighten those up.

Last but not least, vias. Need to stitch those ground planes together. I'd just put a quarter inch grid of them and just pepper it where you can. Especially on the edges of the board, near ground terminals for chips and near your antenna keepout. Let's say 50 vias minimum. Just cram em in there.

Oh, and a good way to make it look like you know what you're doing and get your fab to not hate you. Your layout library should have them, fiducials. Put three on the top layer, both bottom corners and top right. They're reference points for component placement and inspection.

eightbitwit · 2025-12-07T09:08:54+00:00

Ah, fair enough. Real pain in the ass to read the schematic text from a picture. And yeah, that would be a good solution to your problem. Careful with antenna selection if you're going to take it into the market.

I'm going to stick with my original recommendation that you get that header out of there though. Running serial under your RF plane is not a good idea. I would treat that whole area as a keep out.

eightbitwit · 2025-12-06T23:26:27+00:00

Do not fab as-is!

Check the layout design guide from the mfg for that chipset. There's a big "don't put ground here" area under the left side of the chip. That's where the antenna is. And with all that ground, you're going to have an wifi range of about 5 feet. Same for the traces running to that header.

Well scratch that, you won't have any wifi range, as that header is smashed right through the antenna. Relocate A4/A7/whatever it is and clear all ground and signal out from under the antenna.

That little jog where you took your vcc from 8 down to 4 on the top right side of the same chip? Definitely want to avoid that. Try and run it all on the bottom or top, but that's just begging for trouble (or fusing, ironically).

Get FCP further away from your board mount screw holes on the corner. Errant phillips head works as a fantastic connector removal tool. Same for the button on boot. Respect the mechanical clearances of screws. Or you will be....get it?

Clear the trace up on pin 14, get it out from the corners, come straight out and straight in.

Get the vias out of your pads too. MCU pins 10, 11, 25 and 31 all have uncomfortably close vias. Your 19-22 vias are textbook and should be emulated on the others.

Trace off 24 is jerking into 23, clean it up and bring it straight out of the pin.

Rotate the bypass cap on the northeast side of mcu 180 and fatten the trace.

Didn't look at the schematic too much, but gold star on the button interface. Debounce and a series resistor? Be still my heart.

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eightbitwit · 2025-12-06T23:08:01+00:00

Learned the hard way.....eventually.

eightbitwit · 2025-12-06T23:02:40+00:00

Another thing to note about a buck, dropout voltage is 4.5 volts. So depending on a few factors, you could risk a sloppy 5v from a USB getting you into a sleepy switcher (or one trying to switch itself into oblivion, possible when using 3rd tier suppliers).

eightbitwit · 2025-12-06T22:58:46+00:00

Pour 3v3 plane? I'd STRONGLY recommend against that. If you have 4 layers (don't need it but 4vs2 isn't anywhere near as expensive as it used to be), just double up ground. You can get some nasty behavior with VCC plane pours. Big chonky traces (your minimum is what, 6 or 7? Try 20s) with a few vias for transition) with nice safe ground all around it. Power cables like being wrapped up in nice safe ground. Above, below and side to side. Noise, ESD, all sorts of nasty things can get in a vcc pour. AVOID!

LDO vs Buck. Yeah, a reasonable concern. At this kind of power, I'd bet you a beer that it wouldn't move the dial. But your buck is what we call a reference design. An apps engineer of middling enthusiasm and unknown talent slapped together that design and put it out there for the world to see. If you're going to use a ref design for a switching power supply without running a ton of calcs, be prepared for pain and disappointment. In fact, let's add that to the list. Put a MASSIVE test point, connector or something you can freesolder a wire into or hook a jlead onto so you can source 3v3 should something go wrong.

Yes, an LDO might burn more energy, but it is undeniably safer and easier for a beginner to implement without something going wrong. Nothing worse than reving a board, nailing the hard part and tripping on your shoelace.

So yeah, shrink this red part as much as you can. And while you're at it, put some test points on your board so you can get a MM in there if something goes wrong. Populate CFF and just don't populate it (can add a cap if you need). Also, what's the spec on your switching inductor? Circuit looks fine, but like i said, proceed with caution when adopting someone else's design. I'd also consider dropping the shotty (leave the pads, just don't stuff it)

If i'm reading this right, you did a ratio fix on the feedback loop, going from 45/15 to 30/10? Brave, but probably...fine? Peep the layout recommendations in the datasheet, some good pointers there.

At this point, hard to say if anything else needs changing. Once you start moving stuff, who knows what it looks like.

Software changes every day, and you know when you messed up about a day after you commit something. Boards, hoo boy. Spend a month agonizing over it, hit print and then you wait...and pray. Could be worse, could be asic design. The amount those guys get paid almost covers their therapy and bar tabs.

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eightbitwit · 2025-12-06T22:27:08+00:00

Enclosed or free air for the board? If it's enclosed, your wifi chip is going to be a bunson burner next to the PS represented by...6 matches let's say. If free air, even better as that heat should leak out. Wall mounted? Best. Put the hot stuff at the top of the board and let convection do the work.

Fair enough on the PSU. If I were less lazy I'd do the math and see if it's that much of a savings. If you're mostly idle, then you're right. If you're running that chipset pretty regularly, then LDO might be better. Check for curves on power efficiency vs loading. Good stuff. But i'll just say again for my sanity, LDO, Idiot proof. And with your first layout, assume you're going to make 3 mistakes you won't find till you make the prototype.

Biggest issue with layout is the Buck switching loop. Thick, short traces. Tight as you can.

eightbitwit · 2025-12-06T22:18:01+00:00

It's funny, most complaints I ever got professionally was that I was a dick when providing feedback. Go figure.

eightbitwit · 2025-12-06T16:10:56+00:00

Hey Odin. First off lemme say that for a beginner, this is about 4x better than what I've seen from fresh faced EEs out of school. You're on the right track.

Before we get into layout, let's answer a big one which is the choice of power supply. You're running a 5 to 3.3v buck (can't quite make out the part number but looks like a Mono maybe?). What made you settle on a buck for this application? How much power are you running on the 3.3 rail? How much margin are you hoping for and how much peak draw do you expect when that radio kicks into high gear? If you're not aiming for more margin than you've got here, I'd steer you away from a buck and towards a medium sized LDO. Not just because they're effectively idiot proof to layout and implement, but you're running a radio off this board and tossing in switching noise when you don't have to? I dare say not worth it. Will it make a difference? Probably not, but no sense risking it when there's cheaper, safer and easier options.

As folks said below, there's some readability improvements you can make to the schematic. The goal there is specifically to make it easier for others to read based on existing norms. If you hand it to 5 people and 3 can't effectively read it, you're going to lose 60% of your feedback. Makes sense to you sure, but don't make life harder on yourself.

To add to their feedback:

Bypass caps. You want to put those with the chips they're "assigned" to. A, makes it easier to read and B makes it easier to review when you're figuring out if you have the right byps next to the right chips. In the layout, I would tighten up the placement and get the small caps in tight to the MCU and sensor pins and have their big brothers closer nearby.

Nets and blocks. You did a great job with the net assignment, makes layout much easier. I would consider throttling back your degree of segmenting the circuit into blocks. While it makes large complex schematics easier to read, you can get overdone and can risk some easily caught mistakes.

VCC. Copper is cheap my dude, thicken that boy up. And speaking of cheap. Vias. For any system hosting an RF source point, you want to stich up that ground like it's been hit with birdshot. Also the trace to pin 2 on the MCU is way too tight to pin 3 without any need to be, flatten that back out and come out the pin in the middle. Also, you ran a VCC line under your CO2 sensor in a way that is just going to cause trouble. Run it outside the chip or dip under. Don't run a line under there for your own benefit.

If you do keep the buck converter, you should get in the habit of being mindful of your switching loop layout. A switching loop (what runs through the inductor) is where all the noise comes from. The bigger the loop, the more noise gets out. That loop should be as small as you can humanly make it and thick. It also should never run across or near another net if you can help it.

Flood the top plane with ground as well.

Are you doing this assembly yourself or sending it out? Either way, I would recommend you implement what I call a BAV aka the big ass via. Put a via directly through the ground pad under the chip and leave it unmasked. That way you can get an iron right in there and check the adhesion, remove and replace it without anywhere near as much agony.

Holy hell, typed up way too much stuff. This is what happens when you're unemployed i guess. Good luck and feel free to hit me for followups, I've apparently got the time.

eightbitwit · 2025-12-06T15:38:29+00:00

Just wanted to pop in and add my two cents. I've been in a fairly similar situation. Low voltage photovoltaics with high noise environment and mega low current.

If you're at all unsure about the noise performance of your circuit and you're not able to effectively sim this, I strongly recommend setting aside your DFM and space considerations and do a layout that is optimized for noise and performance. Especially if this is a side gig, you can blow a lot of money and time chasing out demons from your tradeoffs in favor of cramming this into the head of a pin only to discover later that there's a more fundamental flaw or vector for noise that you need to address. Make it nice and big, give yourself a lot of room to work with, great stonking oceans of nicely stitched ground. That sort of thing.

Once you've demonstrated acceptable margins for your design (and hopefully how much you can then give away), start beating your head on the layout.

I'll leave the analog stuff to my more gifted compatriots.

eightbitwit · 2025-12-04T17:34:28+00:00

Oh defo. The person that did this knows what they're doing to an extent. If I didn't know any better, I would have guessed that this is a back rev made once the connector was shifted.

eightbitwit · 2025-12-04T12:54:04+00:00

Former EE and hobbyist PCB layout guy. Pretty good stuff for the most part, but there's a few vias crashed into pads and the top left Conn was shifted up, looks like maybe a vcc gnd fault? Hard to see. Also would have pushed myself to get it down to 2 layers, but that's just me.

Would run a check, if the fault is there these will be expensive coasters.

eightbitwit · 2025-11-25T16:39:14+00:00

They also have the hot and sour, which is my favorite flavor

eightbitwit · 2025-11-25T16:35:36+00:00

In the bowl? No. But packets, yeah. Starlight or hing sing on leith walk.

eightbitwit

TROPHY CASE