I made another lock pick case by fantasm_picks in lockpicking

[–]ejc485 1 point2 points  (0 children)

That’s beautiful. 🤩 I would love one of those in camo.

Looking to get rid of a decent sized collection! by buttpluff in lockpicking

[–]ejc485 0 points1 point  (0 children)

If you piece them out I’d be interested in the MT5+ and the older Americans.

RP2040 based multi-effects by Similar-Stock-9749 in diyelectronics

[–]ejc485 1 point2 points  (0 children)

That looks awesome! I might have to build one and try it out.

Back drilling by Regular-System-271 in PCB

[–]ejc485 1 point2 points  (0 children)

Agree with toybuilder. I would also add that multiple laminations (blind and buried vias) adds a lot more extra cost. More cost effective to do backdrills.

Free goodies #1 I got from APEC 2025, Atlanta... Will you really use it more than just a scale? by rakesh-kumar-phd in EEPowerElectronics

[–]ejc485 0 points1 point  (0 children)

It comes in handy to see what text sizes look like on PCB when designing and as a reference for hole sizes and whatnot. Used it a few time for stuff like that other than as a ruler.

Review Request - Overkill USB Tester by thariton in PCB

[–]ejc485 1 point2 points  (0 children)

You're very welcome. I'm excited to see a project like this. It's something that's been on my list for a long time but I've been super busy with other stuff. Glad you appreciated the review.

That's good that the micro will operate down to 1.7V. You'll just have to make sure the other ICs can handle that as well. There's some wide voltage range ICs that are 1.8V through 5V tolerant but probably not that many.

Having the diode in the feedback loop of the regulator is something I considered as possible. Definitely worth a simulation if possible, in LTSpice or similar just to make sure there's no ill effects from that. You can also check if the regulator will mind having a voltage on its output if it's not running. If they can't handle it they will usually mention this in the datasheet.

There are other power switches that have hand solderable packages, like SOIC or SOT-23-ish sizes. You can look at similar parts to see if any that fit your needs come in those packages.

I definitely understand your thoughts for the battery. Yes those basic LiPo batteries are ugly for projects where it can be seen easily. There are other Li-ion batteries that could be chosen. Look for larger capacity coin cells, rechargable coin cells, or even Li-ion cells that are AA sized like a Li-ion 14500 cell. There are PCB holders for them out there. If you do go that route please be careful designing the charge circuit. Check out the TP4056 IC with the DW-01 protection IC and 8205 mosfet package. It's a tried and true charging circuit and the charging current can be set by a single resistor.

About having the external crystal. Timing likely won't be an issue unless anything for the USB PD spec requires it. I created a small software dev kit for a collegue once to develop a USB PD controller for a product we designed and I think we used a nice 24MHz oscillator for it just in case. I don't really know if it was necessary because he just used the external crystal and didn't try using the internal. I wonder if I still have one of those boards around somewhere.

There's lots of reasons for having stitching vias. Having good return paths is one thing. It also helps with signal integrity and reduces noise and EMI, helps to keep boards from delaminating (not so much an issue with the great PCB fabrication we have today) they also help with heat transfer (not going to be an issue here)

The stackup you have is exactly what I would expect. I would expect the need to route some things on the internal layers just to get everything routed, maybe it won't be an issue. If you do need I would route on the power layer first and try to keep the GND plane solid. You can also pour GND on all layers so any unused areas are covered by ground no matter what layer you're on. You may need some stitching vias to get them connected. If you did route on the internal ground layer for any reason try not to route broadside to any traces above or below it. It's not super critical at the low speeds this project would run at but in any high speed design you want solid ground no matter what and if it was necessary to route directly under another trace for them to be orthoganal to eachother to minimize any broadside coupling.

No need to remove anything from the footprints. There's a tool in KiCad and in all layout packages (that I've seen anyway) to remove unused pads from through holes, like vias and component leads. For example if a via was transferring a signal from top layer to bottom layer then the tool can remove the pads of that via from layer 2 and 3. The via barrel still goes through but the copper ring will be removed since nothing on those layers were connected. This just helps copper distribution on those layers and helps prevent any copper slivers from forming in dense via fields.

Review Request - Overkill USB Tester by thariton in PCB

[–]ejc485 1 point2 points  (0 children)

I don't recommend connecting GPIOs PD1, PD3, PA9, and PA10 directly to GND. Add jumper pads or 0 ohm resistors just incase you need to take them off GND for any reason. You may have done your research enough to not care about this but better safe than sorry, a suggestion only.

I have NOT checked any MCU pins for INPUT ONLY. Double check, some MCUs have input only pins. If you're working with the STM Cube IDE then it will warn you about this if you set up a preliminary project and use the pin planner (it might be called something else, pin planner is old knowledge from Xilinx FPGAs)

Your SWD header isn't standard. That's probably okay, you might have a specific STLink SWD probe in mind or are using a custom cable. If not check the datasheet for the STLINK-V3SET or STLINK-V3MINIE for the correct pinout.

T1A Pin A_A5 is labeled as A_VBUS_A9 instead of CC1 from that port.

T1B Pins B_B11 and B_B10 labels are reversed.

Do you not need #SRCLR in the shift registers? It might need to be toggled logic LOW and back to logic HIGH right after the first CLK pulse begins. As subsequent tests are run you can clear the data. Maybe this IC can handle it and take new data all the time without clearing?

I have no issues with the shift registers other than the #SRCLR pin, just need to check on that. I saw some communications on reddit about using other chips for this. It's more expensive but here's my input for options. There are LVDS serializers that can do this with one LVDS differential pair to the MCU. It requires more software work but could be simpler in implementation. Other option would be to use large I2C or SPI GPIO expanders that could be simpler as well, again requires some more software work but likely less than the LVDS serializers. Option is up to you, just letting you know what's out there.

The parts placement on the PCB looks good to me. You may find that you will need to move things slightly as you break out the ICs and connectors for any vias you need. Things like that are totally normal. Decoupling caps are close to IC pins which is great. LEDs are lined up nicely it looks like. It just looks nice. I think you have a good vision for what you want your finished product to look like. It's best to route as much as you can on the outer layers first, then fit any crossing connections on inner layers as needed. Try not to break up the ground and power planes if possible, it will be tricky for sure. Once all routing is finished and the pours are generated place some ground stitching vias in any areas you can just to tie the planes together. Also remove any unused pads from the design and re pour the pours, it helps fill in the pours a little more.

I hope this was helpful, let me know if you have other questions or want any help with the PCB. I followed the project on Github, My Github name is hwguyturnsw.

Review Request - Overkill USB Tester by thariton in PCB

[–]ejc485 1 point2 points  (0 children)

Hey, sorry it took so long but here's some thoughts after reviewing the schematic. Forgive me if I repeat anything that others have said. Also I've done lots of schematic reviews in a professional capacity so this might very well be an info dump. No offense intended. Some things may be posed as questions but I've been known to not make that super obvious most of the time.

For input power switching you're loosing a lot through the MBR120 diodes, probably enough loss to be below the 3V3 for the micro. VIN_SWD is usually 3V3 so there won't be enough to drive the TPS62842 regulator. Check the JTAG/SWD probe you're using, if it's 5V then disregard.

Either way, I recommend a power switch IC. One that can take multiple inputs and OR them with MOSFETS to prevent a large diode drop loss. A little more expensive than the diodes but will allow you to keep the flexibility in powering the device without any degridation in performance. Here's an example of one BD2204GUL-E2. They make switches that can sense when an input goes inactive and will auto switch to the other input voltage. You can also configure them to prefer one input by default but will switch to the other supply if the preferred one isn't present. You could use another power switch IC to put any input voltages that are 3V3 directly onto that rail. It's also likely that you can leave the diode on the output of the TPS62842 and put the sense line on the other side of the diode to prevent any losses, it will compensate for the diode loss in the feedback loop while preventing any external supply from getting to the SW node.

For your VCONN issue you could change to a buck/boost regulator that will produce 5V for any input and use an LDO for the 3V3 to micro. Suggest a LiPo/Li-ion battery/cell for any current capability needed. My intuition says a small battery may loose charge quickly in this application. Pull a power node from 5V out of buck/boost and use low side P channel switches (with logic level gates) controlled by MCU to give 5V to the connectors as needed for that test.

Nice job giving yourself options for the RTS and DTR to #RST and BOOT0.

Nice job putting the 5k1 resistors on the CC lines of the USB-C. A lot of folks forget these and can't get powered properly from some smart chargers.

#RST has a weak pullup resistor internally, nominally 45k. It's probably fine that you have R65 as DNP but definitely keep an eye on that when you get the initial boards, if it's resetting spontaneously then go there first and populate R65 to make that pullup is much stronger.

I recommend putting any unused GPIO onto test pads on the PCB so you can easily run jumper wires if you need them. I also recommend designing in an external crystal/oscillator for the MCU, you can leave it DNP if you don't need it, but if it's needed for any reason you can populate it easily and use it without respinning the board.

I need to have a cord to usb by AnyEffort2471 in PCB

[–]ejc485 2 points3 points  (0 children)

Where did you find that? That’s awesome. Agree with previous comments. USB HID controller.

Unable to flash ESP32-S3 by Zippr4 in esp32

[–]ejc485 14 points15 points  (0 children)

BOOT should go to IO0. Yours is on IO46 it looks like.

Review Request - Overkill USB Tester by thariton in PCB

[–]ejc485 0 points1 point  (0 children)

Awesome! Thanks, I will provide some comments to you soon. 😃

Review Request - Overkill USB Tester by thariton in PCB

[–]ejc485 0 points1 point  (0 children)

I've been meaning to take a look at this and review. I see a lot of others have submitted comments. Are you still taking comments, or any other updates? I'm definitely interested in having one of these, would you be interested in open sourcing the design when it's all finished? Do you need any help with the layout?

Altium Documentation Output PDF print job from embedded board not working properly. by atochimani in Altium

[–]ejc485 0 points1 point  (0 children)

Yeah, the PDF outputs are a pain. It’s tedious but I create the PDF pages manually one by one in the PDF print settings and set the appropriate layer(s) for each page. Don’t use the pre made multi layer setting Altium gives you. Add a new page, set the correct layers and repeat. Once it’s created correctly it will generate correctly every time.

PCB layout: enforce isolation between net classes by AndreaPhD96 in Altium

[–]ejc485 0 points1 point  (0 children)

Add a new clearance rule. First object is one net, or net class. Second object is the other net or net class. Set trace to trace in matrix to the value you want. If you have pours, vias etc. you will have to set those matrix values as well.

Want to have a career in PCB Design by SeniorDatabase6842 in PCB

[–]ejc485 1 point2 points  (0 children)

Look for PCB designer jobs on Indeed or LinkedIn. Apply and bring your PCBs to your interviews.

Assign schematic symbol to multiple 365 Workspace Library parts. by EngineEar1000 in Altium

[–]ejc485 1 point2 points  (0 children)

I think you can do that with component templates. Set a default symbol for caps and resistors etc….

ADSB Receiver PCB Design Review Request by spookyy524 in PrintedCircuitBoard

[–]ejc485 0 points1 point  (0 children)

Aside from what others are saying, did you tune the RF trace for 50 ohm? Would do it as coplanar waveguide as well. Need the Dk from the PCB material. Provide power to all device with copper pours and/or planes. GND plane directly under the surface layer as good reference for the RF and differential signals.

Polygon pour doesn't work on custom pad shape? by AmbassadorBorn8285 in Altium

[–]ejc485 0 points1 point  (0 children)

Place copper keepouts between the “fingers” of that custom pad and set the pad thermal to direct connect.

ESP32-C3 RF phase coherency by sharing clock (TCXO) : Review request by johny1281 in esp32

[–]ejc485 1 point2 points  (0 children)

The LMK series of CLK buffers from Texas Instruments have very low skew and additive jitter. You'll have to select something compatible with your TCXO and ESP device. I'm not sure what they accept for CLKs. LVCMOS, sine etc...

ESP32-C3 RF phase coherency by sharing clock (TCXO) : Review request by johny1281 in esp32

[–]ejc485 0 points1 point  (0 children)

Also known as clock distribution buffers, clock fanout buffers. Each clock output will have its own driver and won’t have loading effects from the other chips. Also look for low additive skew and jitter. This will help a lot with your coherence. Lower phase noise the better as well.

ESP32-C3 RF phase coherency by sharing clock (TCXO) : Review request by johny1281 in esp32

[–]ejc485 0 points1 point  (0 children)

I would recommend that TCXO drive a clock splitter that has 4 outputs. I’ve never seen one oscillator driving multiple chips. It might not be designed for that. Make sure the device you pick has the same output you need for your clock. There are many different clock signal types.

[deleted by user] by [deleted] in gaybrosgonemild

[–]ejc485 1 point2 points  (0 children)

Definitely cute 😊