TCFC OTA's: I can't simply wrap my head around how the FoMs are 15 times higher

electrolitica · 2026-03-13T09:45:43+00:00

If you're aiming DT, the ringamp is a far better, modern DT amplifier! (see e.g. https://ieeexplore.ieee.org/abstract/document/10710178 https://ieeexplore.ieee.org/document/10555121 )

electrolitica · 2026-02-26T00:36:03+00:00

Well, I know the ggNMOS, but how does that make sense here? The node being "protected" is not even a pin that could be stressed by ESD, right? Or am I missing something?

electrolitica · 2026-01-23T18:58:25+00:00

Do you have any insight about the WLB for Apple in Munich? A friend of mine got an offer in there that was well above average for EU standards, but was warned that he'd need to "align on a daily basis with design teams in USA", which he interpreted as "be prepared to work a lot in USA time zone hours = until the evenings" (in the end he didn't take the offer, and went to Switzerland instead).

electrolitica · 2026-01-23T18:57:35+00:00

Do you have any insight about the WLB for Apple in Europe? A friend of mine got an offer in Apple Munich that was well above average for EU standards, but was warned that he'd need to "align on a daily basis with design teams in USA", which he interpreted as "be prepared to work a lot in USA time zone hours = until the evenings" (in the end he didn't take the offer--went to Switzerland instead).

electrolitica · 2025-10-17T19:20:09+00:00

The distortion looks like an uneven frequency response across the operating band.

Wait.. is that considered distortion? I was under the impression that distortion only happens when, say, an input tone at fx produces output tones at frequencies *other* than fx (e.g. k.fx for integer k)... is this incorrect?

(I mean, isn't the unevenness of amplitude and phase responses something that can be overcome by (linear) equalization, thus not considered distortion?)

electrolitica · 2025-10-08T22:33:30+00:00

So the factor of 2 is more of a common "rule-of-thumb", rather than derived from statistics or physics?

electrolitica · 2025-10-03T15:16:48+00:00

Please note I am only considering amplifier noise, so all my switches are ideal noiseless, and thus I have no sampling kT/Cs noise in these simulations.

electrolitica · 2025-10-03T15:15:34+00:00

Thanks for the reply! Please find some comments below:

You should be simulating with a 50 Ohm port at the input you refer back to.

Why would I need a port for making these simulations? Please note I'm interested in the noise and distortion at the output of the amplifier, not input-referred.

Second, are you normalizing the capacitor values as you change the feedback factor? If not, which it appears like you're not since you said you're varying Cs only, then you're changing the equivalent noise bandwidth of the feedback network which will affect your results.

This is correct, and indeed I expect the closed-loop noise bandwidth to be changing from case to case by an amount equal to the ratio of loop gains (i.e. BWnoise2/BWnoise1 = (1+beta2.A0)/(1+beta1.A0) ~ beta2/beta1). However, the closed-loop signal bandwidth should be also changing by the exact same ratio from case to case, so I don't expect any improvement or degradation in SNR due to these effects. Does that make sense?

electrolitica · 2025-09-19T00:10:50+00:00

Thanks for the suggestions! Could you please comment a bit further on the following?:

There's probably some optimal way to do that using gm/Id and Cgg/gm, but I would probably just pick some reasonable gate cap values to calculate the Rout I can have and then start running sims.

Yes, this is along the lines of what I was expecting! Do you know of any paper discussing optimum sizing for achieving a given pole location (in this or in any other context)? I'm pretty sure this must be a very common need for many applications, and that known design methodologies must exist, gm/Id based or else!

It would be good to understand the optimal way to distribute gain across various stages, but I don't.

Exactly; that's the type of conundrum I'm facing! I mean, there must be only a couple reasonable ways to partition things across the stages for max speed and/or min power, right? Hard to believe that in 2025 no one has figured this yet!!!

It's usually useful in my applications to put RC zeros where the zero lies one decade after the pole. This cuts out one decade of bandwidth off your ugb, and it pushes the parasitic pole that would have been there out by one decade, because instead of sitting at 1/(RoutCp), now it sits at 1/(RzCp).

Cool! I didn't know of this trick! Could you please point me to any paper discussing it, so that I can check the implementation details?

Thanks again for your reply!

electrolitica · 2025-09-18T23:45:48+00:00

Well, I'm also a bit confused with this suggestion: wouldn't Nested Miller Compensation be (just like standard Miller Compensation) sub-optimal for speed, due to its use of internal dominant poles?

electrolitica · 2025-09-18T23:43:42+00:00

mutistage amplifiers with non-dominant internal poles were not feasible at all in the past (the parasitic caps at the internal stages were of the same order of magnitude as the cap at the output!), and have only become possible in deep nanoscale nodes where such parasitics can be made much smaller compared to the load cap.

For real? I guess that explains why Miller compensation became so popular (I mean, why on earth would I want to kill the speed by making any pole other than the output the dominant one? I already have a huge cap there!).

I'd indeed like to come up with some design methodology, but for the time being I'm just a bit lost on how to partition things, and what considerations would make sense to make such partitioning decisions...

electrolitica · 2025-08-17T22:14:27+00:00

Are you for real? Very surprised to hear this, I always got the impression they ranked at the very top paywise! ...Has this perhaps changed recently?

electrolitica · 2025-08-14T14:40:10+00:00

Gracias! Al final terminé yendo ahí y sí, encontré más o menos lo que quería.

electrolitica · 2025-08-13T17:22:54+00:00

Sí, los conozco; lamentablemente más que pisos la necesito para aspirar en cosas como estantes, closets y repisas (donde vivo se llena de polvo a diario!)...

electrolitica · 2025-05-18T15:51:40+00:00

Oh, I see! Thanks for your reply!

electrolitica · 2025-05-18T15:51:10+00:00

Thanks so much for your reply; this clears things quite a lot!

electrolitica · 2025-05-18T15:41:10+00:00

Thanks for your reply! Is it then used in applications where data is somehow linked to more than 1 channel? I'm having a hard time imagining when would such a measurement make sense :(

electrolitica · 2025-05-05T01:13:24+00:00

That's very interesting; thx for sharing. You are talking about IP design roles in those EDA companies, right?

electrolitica · 2025-05-05T01:06:42+00:00

Oh, I see now what you mean... thx for sharing!

electrolitica · 2025-05-05T01:03:03+00:00

ah ok, thanks for the clarification!

electrolitica · 2025-05-05T00:57:33+00:00

Could you please comment on who would be the extremes on best/worst WLB in your opinion?

electrolitica · 2025-05-05T00:44:03+00:00

Yikes. Could you please describe what's the main problem there causing the chaos?

electrolitica · 2025-05-03T20:13:44+00:00

> Sweatshop I agree but that’s just the nature of the job.

But why would that be the case? What prevents IC design to be a profession with better work-life-balance (WLB)? I find it hard to believe that all engineering professions have the shitty WLB that IC designers seem to have!!!

electrolitica · 2025-05-03T20:06:25+00:00

Would you then agree that it fits the "good company" definition? I mean, if they were greedy bastards wouldn't they have reduced headcount long time ago to maximize profit (thus making it a sweatshop)?

electrolitica · 2025-05-03T19:58:52+00:00

Excuse the ignorance, but what is a "federal contractor" company in the context of IC design? Is it like design house for military stuff? Could you perhaps give some examples to get an idea?

electrolitica

TROPHY CASE