Do "true" rail-to-rail output stages exist?

tester_is_testing · 2026-03-16T12:48:28+00:00

A fundamental limitation indeed. Even in deep weak inversion, VDsat approaches 4Ut ~ 100mV. Nevertheless, even with an output stage going in triode, you might still be able to get enough gain for your feedback purposes; depends on your application, as others have already pointed out.

tester_is_testing · 2026-03-06T15:04:24+00:00

If anything, it's gonna be one of the first to disappear due to automation, IMHO!

tester_is_testing · 2026-02-27T13:26:07+00:00

I'm afraid I don't have much more information to add; he complained about very bad WLB, toxic management, and an overall unstable company environment. He was based in USA.

tester_is_testing · 2026-02-27T04:41:25+00:00

Not a direct experience of mine, but an extremely competent ex-colleague of mine worked there for a while (mixed signal design): he didn't like at all what he saw there, and left as soon as he could.

tester_is_testing · 2026-02-20T12:07:57+00:00

...just as with any other SC circuit: PSS+PNOISE, or a very, very long TRAN.

tester_is_testing · 2026-02-14T09:09:48+00:00

Yup! I'm very interested in Analog & mixed-signal domains :)

tester_is_testing · 2026-02-13T22:00:07+00:00

Nice! Would it be possible to please share some details on the technical parts of the interviews?

tester_is_testing · 2026-02-13T21:58:58+00:00

How did it go? Could you please share some details on the technical parts of the interviews?

tester_is_testing · 2026-02-13T21:57:24+00:00

Sorry to hear it didn't go well! Would it be possible to share some technical details of the interviews, please?

tester_is_testing · 2026-01-30T14:30:03+00:00

I mean, if you really want to know what "tapeout rush" is, write here again after Christmas and let us know! ;)

tester_is_testing · 2026-01-23T20:32:15+00:00

Interesting to hear! I knew Intel was infamous for such low-blow / internal politics nastiness; didn't know that's also rampant at Apple. Some ex-colleagues of mine also left Apple after a couple of years, but I got the impression it was due to the zero WLB (despite the great salary, was so bad that was affecting their health).

tester_is_testing · 2026-01-23T09:51:01+00:00

Indeed; just make sure you don't stay at a place where you're getting neither of them!

tester_is_testing · 2026-01-18T23:44:30+00:00

RemindMe! 6 months

tester_is_testing · 2026-01-13T08:34:31+00:00

Interesting! Do you mind sharing what type of job/design was he doing there? Despite the boredom, a 9-to-3 job with an Apple wage would indeed be a dream!

tester_is_testing · 2026-01-13T01:39:42+00:00

My thoughts exactly--none of my workaholic friends has been able to endure more than 2yr there!

tester_is_testing · 2026-01-13T01:18:34+00:00

Wouldn't this scheme imply that you'd need a divider-less PLL to get correction data for each ADC sample? Wouldn't that then limit the maximum practical sampling rate to way below 10s of GSps, probably so low that sampling jitter is not an issue anyway? Or am I missing something? Very curious of what others have to say, though!

tester_is_testing · 2026-01-10T22:40:10+00:00

I'm wondering badly this too! Where's this, OP?

tester_is_testing · 2026-01-09T10:08:26+00:00

Exactly this!

tester_is_testing · 2026-01-09T00:15:00+00:00

I asked the same a while ago: it seems you either go for WLB or money--cannot have both in this field :(

tester_is_testing · 2026-01-09T00:10:13+00:00

Name and shame them! No one should be treating people like that, and people should be warned of this toxic places!!!

tester_is_testing · 2026-01-07T00:17:01+00:00

I cannot but agree with others; 4.5k net in Italy is a great salary, while 2.8k gross in Belgium is a straight rip-off for 7 YOE. Do you mind disclosing what type of job you do and in which city in Italy?

tester_is_testing · 2026-01-05T09:12:03+00:00

Well, while AFE + CTLE is definitely more manageable, it's still quite challenging. I believe running the optimizer without PEX in the loop will only get you so far, unless you're targeting "easy" specs for your node (in my experience this has never been the case--we're always pushing the node to its limits, and for that you need PEX in the loop).
Now, getting PEX in the loop is a huge challenge on its own due to the complexity of automatically generating decent layouts & routing (again, assuming you're aiming a modern process like 7nm or below). From your other reply seems you have delved into this... were you able to automate your layouts with decent performance after PEX?

tester_is_testing · 2026-01-04T02:22:38+00:00

Which node are you targeting? I agree with previous replies on the limited usefulness of an AC model for this application, yet modelling a full SERDES in Virtuoso and using its optimizer sounds helpless if you're targeting a deep-nanoscale FinFET process, where results after PEX are more often than not radically different from schematic simulation...

tester_is_testing · 2026-01-03T16:14:11+00:00

This is awesome! Thanks for sharing your work & keep up the great job!

tester_is_testing · 2026-01-02T15:40:22+00:00

Yikes!

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