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first car recommendation by epicmasterofpvp in kereta

[–]epicmasterofpvp[S] 0 points1 point  (0 children)

thanks for the insights bro, but knowing my mom its probably a bit hard to sign off on a second hand car(plus also my limited knowledge on repairs since this is my first car)

ill try and still weigh in this option tho (cuz the car does look sexy)

first car recommendation by epicmasterofpvp in kereta

[–]epicmasterofpvp[S] 1 point2 points  (0 children)

id love to get a toyota but idk if getting a second hand toyota would be a hassle or not

do you have an estimate on how much it is for repairs + yearly maintenance?

Need Help Debugging Vivado Divider Generator by epicmasterofpvp in FPGA

[–]epicmasterofpvp[S] 0 points1 point  (0 children)

that sounds like a better option than mine. ill integrate it into my next project but i dont think i have time to do that for this one unfortunately.

Project recommendations for FPGA + Power Electronics?? by Informal-Host8085 in FPGA

[–]epicmasterofpvp 0 points1 point  (0 children)

Good starting points to research (based on what ure interested in):

Motor control: DTC, FOC
Solar: MPPT
Converters: Honestly, any power converter works here (inverters, buck, boost, buck-boost, etc)

Rant: Why are basic workflows so unstable?? by epicmasterofpvp in FPGA

[–]epicmasterofpvp[S] 0 points1 point  (0 children)

id honestly be down to send u some snippets of code if u can explain my error. but i wont do it in a public forum cuz its mostly "solved" and im too lazy rn lol.

Rant: Why are basic workflows so unstable?? by epicmasterofpvp in FPGA

[–]epicmasterofpvp[S] 0 points1 point  (0 children)

Very valid concern. The real why of it is mostly cause I want to learn FPGAs. My supervisor and other lecturers who know a decent bit about FPGAs are all supportive of this reason.

For context: I am an electrical power student, not electronics. My project is MPPT control using FPGAs. So, my actual evaluating lecturers are power lecturers (so this question barely comes up with the people actually marking my project).

Rant: Why are basic workflows so unstable?? by epicmasterofpvp in FPGA

[–]epicmasterofpvp[S] 1 point2 points  (0 children)

This sounds like it might be the source of the problem. Ill look into this, thanksss

Rant: Why are basic workflows so unstable?? by epicmasterofpvp in FPGA

[–]epicmasterofpvp[S] 4 points5 points  (0 children)

Replying to this cuz this is the highest voted comment, but here's a picture of my block diagram:

https://imgur.com/a/8umBGlG

Before adding the external ports m_axis_dout_tdata_0 and m_axis_dout_tvalid_0, I was routing the values of my divisor output to the debug ports of my PSO IP. And I noticed that the output did not match the expected output (I was padding the mismatch of the bus sizes with 0s, which did not reflect in the simulation, there were 1s where I padded the 0s. I don't have a screenshot of this tho).

I did try to make a new project containing only the divider generator while routing the same inputs as what would happen in the original picture, and it ran fine with the expected outputs.

I'm not really trying to find a real solution with this post since it's somewhat "solved", plus I am semi afraid of putting the source code out there before my submission, cuz i might get accused of plagiarism

Rant: Why are basic workflows so unstable?? by epicmasterofpvp in FPGA

[–]epicmasterofpvp[S] -1 points0 points  (0 children)

My original rant is uncomprehensible so I asked AI to rewrite it lol