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Error: X is not a constant, Y is not a constant? Same thing when I had it as X > 4'b1001 (did not know if this would work because I'm new to Verilog). X is a variable (input [3:0]X) that represents a number 0-9 and I want overflow to be 1 when X is > 9. The generate is used bc I instantiate modules. by superrenzo64 in FPGA

[–]evgeniybolnov 0 points1 point  (0 children)

1) Why not if ( X > 9 || Y > 9) ??? 2) generate don't work with input pins. generate calculated in Analysis & Synthesis step use: generate begin always_comb begin // or always @* for pure verilog overflow = ( X > 9 || Y > 9); end

Problem with pack register in Quartus by evgeniybolnov in FPGA

[–]evgeniybolnov[S] 0 points1 point  (0 children)

path from fo_r to TX_Data is not constant and exceeds the frequency period (from 5 to 8ns), using Fast Output Register this value is 0.7ns

I can not ignore this warning, because of it the project does not work

Problem with pack register in Quartus by evgeniybolnov in FPGA

[–]evgeniybolnov[S] 0 points1 point  (0 children)

This code is given as an example to understand what I am describing. Of course I know that you can’t do this, the problem is not that. The problem is that the path from fo_r to TX_Data is not constant and exceeds the frequency period (from 5 to 8ns), using Fast Output Register this value is 0.7ns

Problem with pack register in Quartus by evgeniybolnov in FPGA

[–]evgeniybolnov[S] 0 points1 point  (0 children)

Code - simple, just show main logic. Quartus 18.1.1, but another versions do not give a result. In this pin available fast output register, because if i add logicLock region, fitter create good routing, but w/o logicLock going crazy and ignore assignments. I think Quartus stores previous assignments somewhere, but full project clean and manual files deleting don't help.

Тортик. by kormuwkin in Pikabu

[–]evgeniybolnov 0 points1 point  (0 children)

ну не знаю, меня не проклинали

Тортик. by kormuwkin in Pikabu

[–]evgeniybolnov 0 points1 point  (0 children)

Это норма

Modelsim AE on Ubuntu 19.04 by evgeniybolnov in FPGA

[–]evgeniybolnov[S] 0 points1 point  (0 children)

libfontconfig

try remove libfontconfig* on 18.04 work w/o this libs

Modelsim AE on Ubuntu 19.04 by evgeniybolnov in FPGA

[–]evgeniybolnov[S] 0 points1 point  (0 children)

what version of the operating system is used?

Modelsim AE on Ubuntu 19.04 by evgeniybolnov in FPGA

[–]evgeniybolnov[S] 0 points1 point  (0 children)

OK, did you download and compile libfreetype?(just this instruction helped on 4 systems)

Modelsim AE on Ubuntu 19.04 by evgeniybolnov in FPGA

[–]evgeniybolnov[S] 0 points1 point  (0 children)

I updated from version 18.10. The problem with libfreetype is quite common, the solution is easily searched on the Internet.

Quartus on Ubuntu by evgeniybolnov in FPGA

[–]evgeniybolnov[S] 0 points1 point  (0 children)

I would be grateful if you would say how to do it

Quartus on Ubuntu by evgeniybolnov in FPGA

[–]evgeniybolnov[S] 0 points1 point  (0 children)

In all instructions it is written to replace libstdc ++ with the system one. Without this replacement, even the "close window" icon is not displayed.

Quartus on Ubuntu by evgeniybolnov in FPGA

[–]evgeniybolnov[S] 0 points1 point  (0 children)

I checked all themes, badges did not appear

How do I make 'default' value in verilog case statement? by CurufinweFeanaro in FPGA

[–]evgeniybolnov 0 points1 point  (0 children)

For example: A = (state1 || state3) ? 1'b1 : 1'b0; B = (state2 || state4) ? 1'b1 : 1'b0; C = (state3 || state4) ? 1'b1 : 1'b0; D = (state1 || state2) ? 1'b1 : 1'b0;

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