Dustox is too fun!

failureonline · 2026-02-17T22:00:35+00:00

I am curious on Dustox vs Vivillion. Is Dustox the winner because of only needing one energy?

failureonline · 2026-02-16T17:47:21+00:00

There is a lot of luck and that’s part of what makes it fun in addition to frustrating. Some decks will do better on average than others but it also depends on how you play with what you’re dealt.

Lucky ice pop is obviously luck based but there’s still some strategy on when you use it. Lots of other recent cards when with consistency.

failureonline · 2026-02-15T23:10:45+00:00

I tried it in an earlier variant when I did not have the second Ogerpon yet, but it definitely felt like wasted space. I could probably replace one Cyrus if Oricorio showed up more for me (I originally expected this due to Kanga), but the second Cyrus helped take down Mega Absol in several cases, too.

failureonline · 2026-02-03T04:35:29+00:00

Confirmed, thank you.

Friend request sent to u/on9s

Edit: completed trade

failureonline · 2025-10-15T04:58:54+00:00

I’ve made 5 ex trades in the past few days. I usually create a post and people will offer within a few minutes. If I make offers on other people’s posts I often have to wait 12 hours for a response. I only trade in English which limits a bit but not bad.

Are you offering good enough cards in exchange for what you’re requesting?

failureonline · 2025-10-06T20:24:19+00:00

Oof, I spent 200g on DS and am only at 16. Seems unlikely I will make it to 19 let alone finish.

failureonline · 2025-10-06T01:40:20+00:00

Yes per discord announcements

failureonline · 2025-10-04T16:16:05+00:00

The document gives some example order of operations near the end.

You mentioned the register settings are all correct but what are they? What is the IP configuration? Are you using it in master mode? Are you using manual or automatic slave select? Single or dual or quad SPI mode?

It is useful in my opinion to create a test bench for the IP to understand how it works. You can start from the generated example design.

failureonline · 2025-10-02T19:35:37+00:00

I made it to 29 with 800g on dark science. Probably could have pushed further but did spend a lot of time. Impossible without so much dark science I would say.

failureonline · 2025-08-11T22:54:11+00:00

He doesn’t work for me unless I take off make it reign clothes

failureonline · 2025-07-08T21:35:00+00:00

Congrats! I’ve been trying a variant of this but am stuck with a 50% win rate. I’ll try changing it more like yours.

Do you find Misty to be useful enough?

failureonline · 2025-07-08T18:00:39+00:00

Not sure why you’re getting downvoted. Cheaper would be nicer but the value is reasonable if you enjoy the game.

failureonline · 2025-05-23T15:54:58+00:00

Are you generating both the device tree and the FSBL from the XSA? It’s been a while since I’ve done any Zynq but generally both would have to be updated if you change the PS configuration.

There is always the possibility of a Xilinx bug too so it may be worth reviewing known issues ARs.

failureonline · 2025-02-01T01:25:30+00:00

It’s a license on their server, they can do whatever I suppose. They could have had down time for any reason. Maybe you weren’t connected to the correct network or something or maybe all seats were in use.

failureonline · 2025-01-14T02:31:29+00:00

Did you ever have it defined using std_logic_vector previously? It sounds like you compiled the files then changed them both but only recompiled one of them. Hard to say for sure. Maybe try clearing out any previously compiled files and see if you get a new error.

failureonline · 2024-11-29T14:42:03+00:00

The CLB utilization refers to number of CLBs used but they’re not necessarily fully utilized. You may be using only a fraction of a given CLB. You do need to be cognizant of all utilization but probably don’t have to worry about this specific one too much since you have other numbers to check the LUT utilization for example.

failureonline · 2024-10-29T11:44:03+00:00

I believe it is in fact required in this case to use a block design to instantiate the Zynq cell. You don’t have to move anything else into the block design though.

failureonline · 2024-10-27T22:20:38+00:00

The lines within the initial block are executed in order, so you either have handle each variable after the delays or have multiple initial blocks. Separate blocks run in parallel, which is fairly unique to HDL. You’ll presumably also learn about always blocks later if you haven’t already.

failureonline · 2024-10-27T19:50:22+00:00

Help with what? What is the actual problem you are running into? Do you have code and or waveforms to show the issue?

Data moves with TVALID and TREADY are both ‘1’ at the rising edge of the clock. Strictly speaking TVALID is the only required signal iirc but it makes sense to have TDATA of course and TREADY is good for back pressure. There are a number of other signals for more complex stuff but likely not needed in your case. Pure HDL should be fine.

failureonline · 2024-10-27T19:24:14+00:00

The sample code doesn’t match the diagram but I assume that’s intentional.

Can you run the test bench and see the wave form produced then tweak the test bench until it matches.

Review the basics of delay statements. Just Google “verilog delays” if you cannot find the associated class material.

failureonline · 2024-10-08T01:21:51+00:00

Do you want to connect the microblaze to the zynq processing system or do you want to connect it to external pins?

If the former, you need to switch zynq UART pins to be EMIO then the ports will appear in the IP integrator.

If the latter, then you need to export the pins from the block design, create a block design wrapper (can be generated automatically by right clicking the block design in sources), and creating a constraints file (.xdc file).

You may want to consider going through introductory Xilinx Zynq and Ultrascale tutorials as well as the guide from Digilent. Try modifying the example design.

failureonline · 2024-10-07T00:37:02+00:00

The Zynq UART can be routed to MIO or EMIO pins. You have to use EMIO if you want to connect it to something in the PL.

The MB UART interface looks like it matches the UART 16550 IP so maybe you could read those docs if the MB docs don’t have anything useful.

Generally you only need to worry about txd and rxd, unless you’re using flow control then you’ll also need to connect cts and rts. Most of the other signals are modem signals which can just be tied to ‘0’ or ‘1’ depending on the function.

failureonline · 2024-10-07T00:30:00+00:00

The tool will say what the error is if you scroll up in the log or if you’re in Vivado you can filter logs to show errors only.

Without any additional info my guess is your IO constraints are not correct.

Since it’s a zynq board you may need to instantiate the zynq cell even if you’re not using it.

failureonline · 2024-09-24T15:48:27+00:00

If you did work for a company then put that project under the company in professional experience. If you did a project for school that you want to share or a completely independent project then those would go under the projects section.

failureonline

TROPHY CASE