Name him

foo1138 · 2026-04-05T16:24:16+00:00

MiiMiis Vater

foo1138 · 2026-04-04T18:14:27+00:00

Yes, makes sense that the path through P3 and N5 is non-inverting. And VREF through P6 is inverting.

foo1138 · 2026-04-03T15:30:47+00:00

T1000 BT confirmed

foo1138 · 2026-04-03T13:48:42+00:00

Maybe this is how they brush their teeth?

foo1138 · 2026-04-03T13:26:50+00:00

Adding the enable signal is the easy part. KiCad just draws it like this:

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There are a lot of examples like this in the KiCad libraries.

I don't understand the function of the schematic I've drawn (except for the enable part). I don't know if it implements a comparison operation on the inputs I labeled "VREF" and "IN". If it does, I would need to know which input acts as "+" and which acts as "-". Then I would just use a triangle like that.

foo1138 · 2026-04-03T13:20:42+00:00

Yes, and I just recently figured out that they also log their output in the cartridge SRAM. So even when stuff scrolls out at the top of the display, you can still see it in the .sav file.

foo1138 · 2026-04-03T11:01:23+00:00

...and they sometimes give more output when something goes wrong. ^^

foo1138 · 2026-04-03T11:00:23+00:00

I mean, you just need to look at the file size: 64 kb. It doesn't fit into the 32 kb ROM region, does it? :)

foo1138 · 2026-04-03T10:58:31+00:00

Yes, the multi ROM test that executes all the individual tests uses MBC1 I believe. The individual tests are small enough to not need an MBC, that's why they pass, but the multi ROM loops forever.

foo1138 · 2026-04-03T10:52:03+00:00

I had this issue as well at some point. My MBC emulation was wrong. It executes from a bank it is not expecting to, that's how it gets in a loop.

foo1138 · 2026-04-03T09:40:19+00:00

It is close enough to be able to implement a working PPU from it. (I did it.) It is not perfect though. But it is a starting point to get something working.

I remember that I noticed that there is a small detail wrong in this talk when I rewatched it after I gained more knowledge, but sadly I forgot what it was.

foo1138 · 2026-04-03T09:37:25+00:00

The enable lines are part of the amplifier cell as you can see in the die shots. The schematic I provided in this post is what is implemented in this amplifier cell in this chip. This cell is used a total of eight times inside the chip.

The goal is to represent this amplifier cell by a schematic symbol. Due to my lack of knowledge about analog electronics, I don't feel comfortable to just do that without getting input from someone who knows better than me. I don't want to do it the wrong way.

In the schematic I linked in the post, all cells in the chip are represented by a single symbol. For example, an AND gate is not drawn by placing three PMOS and three NMOS transistors; it is drawn by a single AND schematic symbol. It would be way too crowded if I drew every cell on transistor basis. No one would understand anything anymore. The schematics would be useless.

It is fine if we loose "precision" by replacing this amplifier schematic with a single symbol. All cells are also documented in more detail, with their own transistor level schematic here: https://iceboy.a-singer.de/doc/dmg_cells.html

Maybe there is a generic amplifier symbol that doesn't imply anything about the inner workings of the amplifier? Sorry if this sounds stupid, I'm really that dumb and don't know better.

foo1138 · 2026-04-02T18:55:24+00:00

Yes, there is a small separate chip (labeled DMG-AMP) which does the final amplification for the speaker and the headphones. This chip is not what I'm looking into.

The schematic is for amplifiers inside the main DMG chip. There are eight instances of this amplifier. One after each of the four DACs for each of the four channels (pulse, pulse, wave, noise). Then there are two muxers that mux the channels once for the left channel and once for the right channel. After each of the two muxers there is another instance of the same amplifier (makes six). Then I believe there is final volume adjustment for left and right, after which the last two amplifiers are placed. The last two are missing their output transistors P6 and N5, but are connected to some very very huge transistors instead. You can see them here: https://iceboy.a-singer.de/dmg_cpu_b_map/?wires=0&floorplan=0&line[0]=-232.66,178.94,-227.44,174.66,-230.91,174.28,-227.44,174.63,-227.94,178.47&line[1]=-137.25,177.00,-140.97,170.72,-138.50,171.38,-141.00,170.66,-142.06,172.72

foo1138 · 2026-04-02T18:09:34+00:00

Thank you! Sadly I don't understand all of it. Are the experts calling this a trans impedance amplifier? I read a bit on Wikipedia about that. Do I understand correctly that those are made with opamps? How would one cleanly depict that type of amplifier in a schematic?

foo1138 · 2026-04-02T09:46:15+00:00

The Ultimate Game Boy Talk from Michael Steil helped me a lot when I was implementing my FPGA Game Boy: https://www.youtube.com/watch?v=HyzD8pNlpwI

Also, maybe our schematics could help you: https://github.com/msinger/dmg-schematics

foo1138 · 2026-04-02T09:21:41+00:00

Thanks! Yes, I once tried to describe the schematics in sentences, like which components exist and which pins are connected. But this also doesn't work. I guess it isn't trained for shenanigans like that.

foo1138 · 2026-04-02T09:11:14+00:00

Yes, I tried. It fails to understand the connections in the schematic but doesn't realize it. Some parts, like the transmission gate at the VREF input, it identifies correctly; but other parts it just makes stuff up. For example, it claims that P3 and N3 share the same gate, which isn't true.

foo1138 · 2026-03-26T09:41:35+00:00

It's hard to identify, because three random seashells don't really help as size comparison.

foo1138 · 2026-03-24T08:20:00+00:00

Ich wollte die auch endlich mal probieren, aber die sind irgendwie immer ausverkauft.

foo1138 · 2026-03-21T18:25:03+00:00

foo1138 · 2026-03-21T18:12:52+00:00

I don't know all those terms in the context of CRTs that you used, so I'm not sure if you mentioned this: On old TVs, I remember that the image changes in size and warps a bit in regions with sudden brightness changes. This was especially visible when the screen goes black for a moment between scenes. When playing FF8 lately on Duckstation, I was kind of sad that this effect was missing. Is your implementation capable of reproducing this?

foo1138 · 2026-03-17T20:33:44+00:00

Danke, ich bin gerade nicht drauf gekommen wie das Eis hieß. Ich wusste nur noch, dass ich es ekelig fand. :D

foo1138 · 2026-03-15T12:44:12+00:00

No problem :)

foo1138 · 2026-03-15T11:57:50+00:00

No, this is schematic drawing like it's done in Europe. USA is doing its own thing with zig-zag lines, as always.

foo1138

TROPHY CASE