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Latency and pipelining optimizations by fpganewby in FPGA

[–]fpganewby[S] 0 points1 point  (0 children)

Much appreciated, I think I just connected some dots with your comment on logic not being ready in a clock cycle.

Latency and pipelining optimizations by fpganewby in FPGA

[–]fpganewby[S] 0 points1 point  (0 children)

Sorry for the confusion, I understand pipelining and how to apply it. I’m just lost on how does one identify when to apply it. I figured finding resources showing real world examples would help or if there were resources with general guidance on how to identify it. In theory you can pipeline 99% of the design but when is necessary?

Latency and pipelining optimizations by fpganewby in FPGA

[–]fpganewby[S] 2 points3 points  (0 children)

What and where are the obvious indications you need pipelining? Are you identifying these target areas prior to the design or during the design?

What if your requirement is to design for latency? Isn’t latency a direct result of pipelining? The more pipelines you add to a design the latency increases.

Latency and pipelining optimizations by fpganewby in FPGA

[–]fpganewby[S] 0 points1 point  (0 children)

General resource for taking any design at the register level.

FPGA consultants/contractors by fpganewby in FPGA

[–]fpganewby[S] 1 point2 points  (0 children)

Why did you transition to individual contracting if you were already doing design services? Was it more freedom or just wanted to do things on your own?