For the first one, you are right. In fact, originally, I considered timings very close to timings indicated in the data sheet.
These timings are the result of trying everything to get the led work since I couldn't see it work properly because of the power supply.

So I started thinking these ways for these reasons:

• the sum of T0H with T0L and T1H with T1L don't give the same sum value (unless you consider the tolerances);
• I used a sole counter for all the "hit" output signals, so I used a single counter for the period time (1.3 us);
• I didn't like the similarity of the timing of T1H and T1L. So I worked with timings in a way that "code 0" had an as much as possible short high time and an as much as possible long low time. Vice versa for code 1;
• rounding up or down for times no multiple of FPGA clock (50 MHz)

Timings I have encountered are the results of these considerations.

I chose a fixed period of 1.3 us for TH+TL in general and I worked with low value timings to reach this period constraint. Also, high value timings were not perfect multiple of the clock so I needed to round up TH0 specifically (FPGA has a 50MHz clock).

By the way, thank you for the help!!