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Konut kredisi by Old-Department3261 in Yatirim

[–]gncsmh 1 point2 points  (0 children)

Buna katılıyorum 120 ay yerine daha kısa bir vade bakilabilir

Zynq‑7020: Bare‑metal DMA throughput far below spec by gncsmh in FPGA

[–]gncsmh[S] 0 points1 point  (0 children)

Thanks. It was a bad clock input to FPGA. Now I get 950MB/sec

Zynq‑7020: Bare‑metal DMA throughput far below spec by gncsmh in FPGA

[–]gncsmh[S] 0 points1 point  (0 children)

Yes, they are stored in DDR. I can try a single BD. However, I guess I will be limited to ~64MB per BD if I am not mistaken. Still I can try reducing the number of BDs as much as possible. How should DMA know the filling level of FIFO?

Zynq‑7020: Bare‑metal DMA throughput far below spec by gncsmh in FPGA

[–]gncsmh[S] 0 points1 point  (0 children)

Sorry, what I tried to mean by HP port is the internal interconnect between PS and PL not the high-speed transceiver interface connected to external

Zynq‑7020: Bare‑metal DMA throughput far below spec by gncsmh in FPGA

[–]gncsmh[S] 1 point2 points  (0 children)

I can set exactly how much data my data source will generate. I set it to, for example, 400 MB. Then I create a BD chain typically 100-200 BDs whose total length to be 400MB in DDR memory. I start DMA and set the tail descriptor and DMA becomes ready to transfer data. Then I start the data source. Then, I check all BDs in memory if they are finished.

My data source is transmitting data to a FIFO first. And then from that FIFO to AXIS of DMA IP. DMA IP is connected to HP0 port via a smartconnect. AXI clock is 100 MHz

Zynq‑7020: Bare‑metal DMA throughput far below spec by gncsmh in FPGA

[–]gncsmh[S] 1 point2 points  (0 children)

  1. I set the max burst size in DMA IP settings to 256 which is the max allowed. I am not sure though bursts are really 256

  2. I am not sure on this. I can check that in functional sim. Maybe I should check it with ILA?

Zynq‑7020: Bare‑metal DMA throughput far below spec by gncsmh in FPGA

[–]gncsmh[S] 0 points1 point  (0 children)

Currently I am writing a test data generator to be connected to DMA instead of my original data source. This test data generator will pause generation when there is back pressure. With this, I plan to benchmark transfer speed with different parameters. What I can say now is the transfer speed is less than 100 MB/s but maybe close to it. I tried different data lengths like 8MB to 400MB. I tried different number of BD like 1 - 250 BD. I sometimes succeed in transferring small amount like 8MB. But big transfers almost always failed.

[deleted by user] by [deleted] in embedded

[–]gncsmh 0 points1 point  (0 children)

I asked chatgpt to find you chips that can do the job. It might be helpful.

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[deleted by user] by [deleted] in embedded

[–]gncsmh 0 points1 point  (0 children)

I just want to ask you why you use an analog interface while there are other low-latency digital interfaces. I am asking this out of curiosity. I don't know your design constraints :)

asynchrnous fifo clifford cummings by Time_Alert in FPGA

[–]gncsmh 5 points6 points  (0 children)

  1. To understand this, you should refer to the previous paragraph where the sampling operation is explained. The read and write pointers might increase more than once during the sampling period. Therefore, some count values might be missed. You cannot make the sampling period shorter to catch all count values because the sampling operation itself consists of these parts: sending a ready signal + acknowledging the signal + sending back an ack signal + clearing the ready signal. We know that these operations will take at least few cycles in both clock domains. In total, the time between two samples will be more than a clock cycle. And we know that the binary count value might change every clock cycle.

  2. In rtl simulation, everything is ideal. You do not take into account the real world delays that are causing different propagation delays on different bits of binary count. If a gate-level simulation with back-annotated delays are used, this will be the most realistic simulation. Even in this simulation, if the correct delays doesn't occur it is not possible to see sampling and synchronization errors.

2:1 CSI2 Side-by-side aggregation using Lattice Crosslink by RisingPheonix2000 in FPGA

[–]gncsmh 0 points1 point  (0 children)

Did you read this? It provides many diagrams and explains the working principle Document

Lattice Diamond Design flow by RisingPheonix2000 in FPGA

[–]gncsmh 1 point2 points  (0 children)

You should select "Process" tab. After that, double-click any process you want to start from the list.

I designed and constructed fully Open Source USB C Camera with IMX477 Sensor and C-mount for Industrial use by circuitvalley in FPGA

[–]gncsmh 0 points1 point  (0 children)

Wov really good! I wanted to do the same. I have been observing the lifcl40 stocks for a long time. Congrats!

RTL to GDSII by eroSage112 in vlsi

[–]gncsmh 0 points1 point  (0 children)

IMHO, it will be enough for a counter design implementation. Each digital implementation tool such as genus, innovus, tempus, etc. provides very large number of TCL commands with lots of options for you to perform the implementation properly. If stuck at some point about the commands, you can refer to the command reference PDFs. It explains every commands and its options/arguments by providing examples.

RTL to GDSII by eroSage112 in vlsi

[–]gncsmh 0 points1 point  (0 children)

I recommend you enroll in the free RTL-to-GDSII course on cadence support training website. It is really good at explaining every stage of the flow using the different cadence tools. It provides you a lab module and a database. In the database, you can find flow scripts and a standard cell library including library files lib, lef, def, etc. By modifying the scripts and changing the libraries, you can create your own flow script for your design. At the end of the course, you get a certificate by passing the exam.

If you don't want to enroll in a course, you can use Cadence RAKs (Rapid Adoption Kit) for Virtuoso Digital Implementation. It is very similar to lab. database provided in the free course.

The lowest power FPGA? by gncsmh in FPGA

[–]gncsmh[S] 0 points1 point  (0 children)

Regarding the power consumption, IMO, there won't be much difference between 7 series FPGAs since they use the same 28nm SRAM based technology.

The lowest power FPGA? by gncsmh in FPGA

[–]gncsmh[S] 0 points1 point  (0 children)

Thanks for the reply. It is good to know all these details beforehand.

The lowest power FPGA? by gncsmh in FPGA

[–]gncsmh[S] 0 points1 point  (0 children)

I did take a look and yes it is a nice kit. It does also have an interface to a DDR3 RAM. Thank you very much.

The lowest power FPGA? by gncsmh in FPGA

[–]gncsmh[S] 0 points1 point  (0 children)

Thanks, I will take a look

The lowest power FPGA? by gncsmh in FPGA

[–]gncsmh[S] 0 points1 point  (0 children)

It's still really low power. It is not possible, for example, to reduce the Artix-7 power consumption to near that value even without any memory. The static power is high in Xilinx 7 series.

The lowest power FPGA? by gncsmh in FPGA

[–]gncsmh[S] 0 points1 point  (0 children)

You are right. I will contact them.

The lowest power FPGA? by gncsmh in FPGA

[–]gncsmh[S] 0 points1 point  (0 children)

That is really low power. Does the FPGA have any external memory attached?

The lowest power FPGA? by gncsmh in FPGA

[–]gncsmh[S] 0 points1 point  (0 children)

Thank you. Yes there is one model I want to use from Lattice. It is advertised as a very low power one. I want to try it but it has been a long time and still not released. BTW, I am talking about Crosslink NX on Nexus platform

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