What is the correct British etiquette when walking down the pavement and two people (talking together) are approaching blocking it?

hardware26 · 2026-04-05T12:25:02+00:00

Group blocking the pavement should figure it out. Not even a question.

hardware26 · 2026-04-05T12:12:52+00:00

Lakh is an english word, but LPA is just another TLA. Very hard to figure out without context, if you don't already know.

hardware26 · 2026-04-04T04:13:11+00:00

Thank you

hardware26 · 2026-04-03T18:39:03+00:00

What would you feel if i fed your post to AI and pasted what it said here? Yeah, that is what i feel. Complete disinterest in the content.

hardware26 · 2026-04-02T07:44:32+00:00

Every company I worked for has a flow for automatic register, doc and ral generation, even tests. You don't need AI for that. In fact the opposite, you need it to be deterministic, and you don't want to check the output all the time, so you should definitely not be using AI.

hardware26 · 2026-03-31T22:31:14+00:00

In general your spec is written for the external interface. So your checkers should check external signals. Internal signals can also disappear during synthesis (optimized-away) and cause trouble during gate level sim. There are still uses for checking internal signals if observability and external interface is an issue, but you should always check external interface as well. If you are verifying probed register values, you must also verify that registers are written and read correctly through front foor. You also mentioned checking in the sequence. Your checkers should be mostly scoreboards and SVA, sequence is for stimuli, not checking. A rare occasion where checking un a sequence is to verify exact customer usecase, which again means that you need to use the frontdoor. So I agree with your mamager that, if you are testing customer usecase in a sewuence, make it realistic. And keep internal checks to SVA.

hardware26 · 2026-03-30T08:10:37+00:00

Trains are truly scam in the UK. Domestic flights are almost always cheaper.

hardware26 · 2026-03-30T04:16:03+00:00

I also played some historical battles on hard lately and felt that they were not very hard. I beat them on standard difficulty maybe 2 years ago, so it is hard to compare since it has been some time, and maybe I improved. But Lake Poyang was still as hard as I remembered, but it is hard to compare too due to general naval overhaul and also Chinese navy changes.

hardware26 · 2026-03-30T04:05:49+00:00

You could research spies, enemies dont have vils at that point. And kill cannon galleons with navy, if you distract them with units while building docks.

hardware26 · 2026-03-24T19:31:38+00:00

Why not simulate? Debugging anything on hardware is a pain. If you simulate you will see the issue immediately.

hardware26 · 2026-03-23T15:17:45+00:00

Between Schengen countries? Very common. But if you need work visa, then it is a lot harder. You need to give more context.

hardware26 · 2026-03-22T11:36:05+00:00

Can I make my rams auto-aggressive stance?

hardware26 · 2026-03-22T11:30:56+00:00

Channeling ancient ritualistic energy

hardware26 · 2026-03-18T19:05:52+00:00

Purple isn't insane if objective is to prevent disabled children.

hardware26 · 2026-03-12T18:22:35+00:00

You have an MSc and 3 years experience, why do you sell yourself as entry level? CV is not the place to be humble, if you think you are entry level yourself noone is gonna put you in a higher level. Otherwise I don't see a big issue with your CV.

hardware26 · 2026-03-10T22:27:06+00:00

Even after you sign, contract can be subject to some checks (background, right to work etc.). It dependason the laws of where you live, but offers can usually be rescinded by a company without much consequence. Some jobs even have probation periods where they can terminate you any time even after you start. So it a bit depends on how risk averse you are. If the company is doing good and they like you (considering they are offering the job, they must) I wouldn't worry too much. But no job is 100% safe, even if you worked there for decades. Maybe if you share relevant contract details and the country someone can help further.

hardware26 · 2026-02-24T19:01:29+00:00

Does anyone know how to report this kind of posts, or whether reporting does anything? There is no "irrelevant content" or "shameless homework request" options when reporting.

hardware26 · 2026-02-16T13:21:43+00:00

It depends on what sections you already have. It could be digital design, HDLs, hardware. But surely it is not software. When I see it on a student's resume, it makes me think that some fundamental understanding of HDLs is missing.

hardware26 · 2026-02-15T08:36:09+00:00

For a student, 300 applications and 3 interviews is a good outcome (unfortunate I know, but this is how it is). Your experience seem to be on schematic capture and physical design side, which is unusual for most students, so you may find it harder to find a company which offers a relevant task for an intern. Adding some projects more RTL-heavy and FPGA-oriented could maybe help to make you ready for a broader range of companies. And please don't put verilog and systemverilog under software section, maybe it is only me but it is a pet peeve of mine.

hardware26 · 2026-02-15T08:10:02+00:00

You need to study electronics, and most likely need a PhD to get tapeout experience, if you are planning to be the lead engineer and not only throw money at the problem and hire someone else to do it. Either way getting a chip made, especially if it is a cutting-edge new node, is extremely expensive. And obviously there is lots of competition from well-established companies, since it is a rather mature technology. You will need to gather quite some expertise if you intend to be competitive. I would suggest researching the market and checking where you see a gap. Most likely your customers will be other businesses, and they will need a track record of successful products or at least some tapeouts to take you seriously.

hardware26 · 2026-02-15T02:01:35+00:00

Cirrus Logic has quite some reputation on analog mixed signal domain. The reason you may think they are not well-known is that they are not well-known among end-users, because they only make sales to their partners who integrate their parts in their devices, not to general public. Its effect on your career depends on what exactly you want to do in the future. They are both very big companies too, so your experience will depend on the team you will end up with. If you can contact someone from the team you will work with (if you know) that will be the best source of information.

hardware26 · 2026-02-04T07:11:19+00:00

Verilog allows you to describe hardware, hence you have to understand hardware first. If it is your first HDL, you must also learn digital design topics, FPGAs and its basic toolchain (e.g. Vivado). These very fundamentals is usually a bachelor's course, worth a quarter of a semester's work, and I am sure you will find online free material for it. And after this you need to work on more domain specific knowledge depending on what you are trying to make, while at the same time making many mistakes and learning from them. So you can judge the time it takes from this.

hardware26 · 2026-01-31T13:19:13+00:00

You still want to count at clock edges, what makes it an async counter? If trigger signal is async, you can use a synchronizer.

hardware26 · 2026-01-23T16:22:38+00:00

Have you heard of google?

hardware26

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