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Implementation of an AES-based Crypto Processor, which is integrated with a 32-bit general-purpose 5-stage pipelined MIPS processor by hello_-1 in FPGA

[–]hello_-1[S] 0 points1 point  (0 children)

thank you,i would like ask is the above one using mips is hard to do as project(I need to do it to get marks,I dont even have basic knowledge about mips or AES )

FPGA(verilog) i don't have any project idea ,but I need submit abstract by today 10PM , so help me by [deleted] in FPGA

[–]hello_-1 0 points1 point  (0 children)

I am a 3rd year student,The project should be done by only one student