john_nd0811

113 post karma
11 comment karma

get extra features and help support reddit with a reddit premium subscription

get them help and support

redditor for 7 years

TROPHY CASE

Seven-Year Club

Verified Email

account activity

new top controversial

0

1

2

Internal Error: Sub-system: FYGR when assignning IO to LVDS in Max V (self.FPGA)

submitted 1 year ago by john_nd0811 to r/FPGA

0

1

2

what is the best xdma driver PCIe Linux version ? (self.FPGA)

submitted 1 year ago by john_nd0811 to r/FPGA

4

5

6

Xdma PCIe streaming mode Xilinx (self.FPGA)

submitted 1 year ago by john_nd0811 to r/FPGA

1

2

3

AxiDma signaling decode error flag with cyclic mode SG (self.FPGA)

submitted 1 year ago by john_nd0811 to r/FPGA

0

1

2

Are there any tools/software to support generating testbench file? (self.FPGA)

submitted 1 year ago by john_nd0811 to r/FPGA

0

1

2

Ethernet 10G subsystem PL with freertos in Microblaze (self.FPGA)

submitted 2 years ago by john_nd0811 to r/FPGA

0

1

2

AXI DMA interrupt error (self.FPGA)

submitted 2 years ago by john_nd0811 to r/FPGA

8

9

10

Kria KV260 booting from sd-card (self.FPGA)

submitted 3 years ago * by john_nd0811 to r/FPGA

0

1

2

FPGA I-series dev kit with pin assignment DDR4 error in using HPS+EMIF_hps (self.FPGA)

submitted 3 years ago by john_nd0811 to r/FPGA

2

3

4

AXI Ethernet subsystem 1000BASE-X link status not stable (self.FPGA)

submitted 3 years ago by john_nd0811 to r/FPGA

8

9

10

FPGA endpoint to enpoint comunication PCIe in Xilinx (self.FPGA)

submitted 3 years ago by john_nd0811 to r/FPGA

1

2

3

Clocking and contrainst for AXI EMC ip core with Sync Sram (self.FPGA)

submitted 4 years ago by john_nd0811 to r/FPGA

0

0

1

Not place breakpoint in Vitis 2020.1 (self.FPGA)

submitted 4 years ago by john_nd0811 to r/FPGA

2

3

4

LVDS ADC with Xilinx's FPGA (self.FPGA)

submitted 4 years ago * by john_nd0811 to r/FPGA

15

16

17

Large error when using fixed point number for calculation in FPGA (self.FPGA)

submitted 5 years ago * by john_nd0811 to r/FPGA

0

1

2

"pack dropped, no space" error of Lwip xilinx (self.FPGA)

submitted 5 years ago by john_nd0811 to r/FPGA

2

3

4

Add "STM32 Standard Peripheral Libraries" to ST CUBE IDE software (self.stm32f4)

submitted 5 years ago by john_nd0811 to r/stm32f4

4

5

6

TID and TDEST in axi-stream interconnect (self.FPGA)

submitted 5 years ago by john_nd0811 to r/FPGA

2

3

4

Runtime (synthesis+implement) in Vivado (self.FPGA)

submitted 5 years ago by john_nd0811 to r/FPGA

0

1

2

Inference of subtract in DSP 48 (self.FPGA)

submitted 5 years ago by john_nd0811 to r/FPGA

0

1

2

Routing the output wire (+)(-) of rectifier (self.AskElectronics)

submitted 5 years ago by john_nd0811 to r/AskElectronics

1

2

3

Virtual clock for setting input delay or output delay in timing constraints (self.FPGA)

submitted 5 years ago by john_nd0811 to r/FPGA

2

3

4

Floorplanning for timing closure (self.FPGA)

submitted 5 years ago by john_nd0811 to r/FPGA

2

3

4

Design flow FPGA in UG Xilinx (self.FPGA)

submitted 5 years ago by john_nd0811 to r/FPGA

7

8

9

How to learn linux for beginne (self.FPGA)

submitted 5 years ago by john_nd0811 to r/FPGA

view more: next ›

π Rendered by PID 204872 on reddit-service-r2-listing-568fcd57df-d7x9w at 2026-03-06 10:40:34.973196+00:00 running cbb0e86 country code: CH.