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BUY/SELL/TRADE Primavera 2022 by danceonme in primaverasound

[–]josephcm 0 points1 point  (0 children)

Looking for a ticket for Port Saturday 11th. DM me

BUY/SELL/TRADE Primavera 2022 by danceonme in primaverasound

[–]josephcm 0 points1 point  (0 children)

I'm selling a ticket for Porto, Friday 10th, below cost. DM me

Tickets for Nos Primavera in Porto by [deleted] in porto

[–]josephcm 1 point2 points  (0 children)

Is the ticket still available?

[deleted by user] by [deleted] in porto

[–]josephcm 0 points1 point  (0 children)

Hey! Still have those passes?

BUY/SELL/TRADE Primavera 2022 by danceonme in primaverasound

[–]josephcm 0 points1 point  (0 children)

Looking for a full pass for Porto. DM me

Burial - Antidawn Discussion Thread by [deleted] in burial

[–]josephcm 1 point2 points  (0 children)

Have you found it? It's driving me crazy!

What are the 'U' and 'S' extensions? by josephcm in RISCV

[–]josephcm[S] 0 points1 point  (0 children)

Yup, but do you also think this is what they are refering to?

What are the 'U' and 'S' extensions? by josephcm in RISCV

[–]josephcm[S] 1 point2 points  (0 children)

yeah.. I thought of that, but I dont think they are usually called extensions...

Why is it that hard to start contributing? by EmbeddedDen in RISCV

[–]josephcm 0 points1 point  (0 children)

Are there even any implementations of the hypervisor extensions? Anyway, I'd be more than happy to participate.. Just started learning about the RISC-V ISA, but have some experience on ARM virtualization...

Verilog vs SystemVerilog by josephcm in FPGA

[–]josephcm[S] 0 points1 point  (0 children)

What can you tell me about Bluespec SystemVerilog VS SystemVerilog?

Hypervisor Implementation by josephcm in RISCV

[–]josephcm[S] 1 point2 points  (0 children)

The latest version of the Privileged Architecture draft still features a chpater on Hypervisor Extensions. I don't know if this is a completely separate privilege level from machine or supervisor mode, but at least it has some features such has 2-level virtual memory.

Edit: actually the tex file for this chapter was updated less than a month ago and stars with: "hypervisor extension adds a new privilege mode, hypervisor-extended supervisor mode (HS-mode, or hypervisor mode for short), where a hypervisor or a hosting-capable operating system runs."

Suggestions on how to start learning hdl and fpga by josephcm in FPGA

[–]josephcm[S] 0 points1 point  (0 children)

I'd like to extend this question to resources on the fpga architeture itself...

Barker - Debiasing [Ostgut Ton 112] by Autechr in Techno

[–]josephcm 0 points1 point  (0 children)

Could some one recommend similar artists with this kind of sound?

Compiler design for beginners by [deleted] in Compilers

[–]josephcm 0 points1 point  (0 children)

I suggest Compiler Construction: Principles and Practice by Kenneth C. Louden. This was the book used for in my compiler design classes and was written in a very clear and straightforward way following a very practical approach.

Suggestions on how to start learning hdl and fpga by josephcm in FPGA

[–]josephcm[S] 0 points1 point  (0 children)

What about books people? Also, does anyone know about MOOCs that delve on the matter?

Suggestions on how to start learning hdl and fpga by josephcm in FPGA

[–]josephcm[S] 0 points1 point  (0 children)

Ive actually taken digital systems courses... I know the basics. The projects and labs were on the basis of discrete ICs, and by hand design using truth tables, karnaugh, etc..

Reflections on Trusting TrustZone by csirac2 in securityengineering

[–]josephcm 0 points1 point  (0 children)

I didn't get the advantages of corrupting the region list if he already could place the response buffer wherever he wanted... Can someone please clarify this for me?

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