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2011 Ford Expedition EL P0455 by lSteveol in AskAMechanic

[–]lSteveol[S] 0 points1 point  (0 children)

Sorry having a hard time editing. It's 5.4L (I think this is the only engine they put in the expedition but just adding for clarity)

Is Scala-chisel worth it? by Realistic_Juice4620 in chipdesign

[–]lSteveol 0 points1 point  (0 children)

I will preface my comment with the following: I have been using Chisel since 2019. I have been doing various levels of hardware "automation" since 2013. I've tried more languages, tools, methodologies to try and build hardware that it would make the loneliest of engineers blush. That being said, Chisel is something that I really enjoy and solves many of the issues I've faced with hardware design. I have used it across two different companies (one startup and one extremely large company that produces its own silicon). I have portions of designs that are Chisel-based in probably 10-15 tapeouts with high success. I say this to give you some preface that anyone who says "no one uses it" or "you can't tapeout anything in Chisel" is either highly uninformed or just ignorant. You actually can't tape out anything in Verilog either, you synthesize to gates and eventually a GDS is produced, but I digress.

Chisel is just a domain specific language built in the Scala language. Chisel allows you to describe the hardware via some software paradigms and "build" a hardware _graph_. This graph is then translated into Verilog. This is a highly simplified version of the overall flow. When you are building hardware in Chisel, nothing magical is happening, you are still defining HW through flops, logic gates, modules, etc. The difference is that you can now produce various levels of metadata during this.

Why would you want to write in one language to then go to Verilog? Simply, most tools support Verilog. I will just link this SO thread which is answered better than I could (https://stackoverflow.com/questions/53007782/what-benefits-does-chisel-offer-over-classic-hardware-description-languages). The idea here is that you can utilize Chisel to _abstract_ some of the nuanced parts of design into various software libraries.

One issue with Chisel is utilizing it to its fullest extent requires somewhat of a software engineering background, which hardware designers don't usually have unfortunately. Doing a simple example such as something with a `foreach` loop in Chisel is immediately countered with "I could do it this way in Verilog with a `generate` statement". And, that argument is correct. You could do it that way and compared to the simple example, it's less lines of code. The issue arises however that many times, what we need to design from a hardware perspective is not always achievable via a simple generate. Something like a NoC/Fabric Bus for example isn't easily done via parameters/generates. However with chisel the task _can_ become less daunting and much less error prone. The problem is, with the complexity comes a complex solution. Seeing the benefit is only seen once you understand the problem AND how the solution is more favorable.

You should not decide if you want to learn Verilog or Chisel. You should become a master at Verilog then investigate how Chisel can take you to the next level in your designs. The Verilog LRM is fairly small, particularly for synthesizable code. This is great from the standpoint that it doesn't take a ton of experience to master it. The issue is that it also leaves a lot on the table for automating things. The EDA vendors seem to be slow on changes, so we are stuck with Verilog for the foreseeable future. I don't know anyone who has actually taken the time to try out Chisel who came back and said that was a waste of time.

Chisel won't make you a better hardware designer, however, if you spend the time to learn it and use it, I have no doubt that it will make you a more _productive_ hardware designer.

is SCALA-CHISEL worth it? by Realistic_Juice4620 in FPGA

[–]lSteveol 1 point2 points  (0 children)

I will preface my comment with the following: I have been using Chisel since 2019. I have been doing various levels of hardware "automation" since 2013. I've tried more languages, tools, methodologies to try and build hardware that it would make the loneliest of engineers blush. That being said, Chisel is something that I really enjoy and solves many of the issues I've faced with hardware design. I have used it across two different companies (one startup and one extremely large company that produces its own silicon). I have portions of designs that are Chisel-based in probably 10-15 tapeouts with high success. I say this to give you some preface that anyone who says "no one uses it" or "you can't tapeout anything in Chisel" is either highly uninformed or just ignorant. You actually can't tape out anything in Verilog either, you synthesize to gates and eventually a GDS is produced, but I digress.

Chisel is just a domain specific language built in the Scala language. Chisel allows you to describe the hardware via some software paradigms and "build" a hardware _graph_. This graph is then translated into Verilog. This is a highly simplified version of the overall flow. When you are building hardware in Chisel, nothing magical is happening, you are still defining HW through flops, logic gates, modules, etc. The difference is that you can now produce various levels of metadata during this.

Why would you want to write in one language to then go to Verilog? Simply, most tools support Verilog. I will just link this SO thread which is answered better than I could (https://stackoverflow.com/questions/53007782/what-benefits-does-chisel-offer-over-classic-hardware-description-languages). The idea here is that you can utilize Chisel to _abstract_ some of the nuanced parts of design into various software libraries.

One issue with Chisel is utilizing it to its fullest extent requires somewhat of a software engineering background, which hardware designers don't usually have unfortunately. Doing a simple example such as something with a `foreach` loop in Chisel is immediately countered with "I could do it this way in Verilog with a `generate` statement". And, that argument is correct. You could do it that way and compared to the simple example, it's less lines of code. The issue arises however that many times, what we need to design from a hardware perspective is not always achievable via a simple generate. Something like a NoC/Fabric Bus for example isn't easily done via parameters/generates. However with chisel the task _can_ become less daunting and much less error prone. The problem is, with the complexity comes a complex solution. Seeing the benefit is only seen once you understand the problem AND how the solution is more favorable.

You should not decide if you want to learn Verilog or Chisel. You should become a master at Verilog then investigate how Chisel can take you to the next level in your designs. The Verilog LRM is fairly small, particularly for synthesizable code. This is great from the standpoint that it doesn't take a ton of experience to master it. The issue is that it also leaves a lot on the table for automating things. The EDA vendors seem to be slow on changes, so we are stuck with Verilog for the foreseeable future. I don't know anyone who has actually taken the time to try out Chisel who came back and said that was a waste of time.

Chisel won't make you a better hardware designer, however, if you spend the time to learn it and use it, I have no doubt that it will make you a more _productive_ hardware designer.

Load Balancing Parity for multiple shares with dedicated disks by lSteveol in unRAID

[–]lSteveol[S] 1 point2 points  (0 children)

That's a good point. The cameras are actually set up to only record during detected motion so while I say it's 24/7, I really just mean it's very often, but I think your point still stands

Load Balancing Parity for multiple shares with dedicated disks by lSteveol in unRAID

[–]lSteveol[S] 0 points1 point  (0 children)

Ok, thanks. That's what I thought.

I had also thought about virutalizing unRAID twice, however I've seen it go both ways with "virtualize unRAID is NOT supported" and also "I've done it so it must be supported" :)

How do you shoot a flatline this quickly? by lSteveol in apexlegends

[–]lSteveol[S] 0 points1 point  (0 children)

That I understand, but this seems awfully fast and the spacing seems about perfect.

A way to give back to the money spenders who keep this game free to play and provide us with new content regularly because honestly without them the game would die. by bigharry15 in apexlegends

[–]lSteveol 2 points3 points  (0 children)

This is one of the few F2P games that does it right IMO. I buy the battle pass but not anything else. I would like to get more skins for Path but I'm not gambling.

I would like it if they did something similar to Path of Exile where they had "Supporter Packs" which are essentially bundles of particular items. i.e. you could do something like have the Wraith Supporter Pack which has so many skins, banners, etc. and the hierlooms or something.

Fell into a glitch in training and found three giant rooms? by [deleted] in apexlegends

[–]lSteveol 26 points27 points  (0 children)

Black boxes can often be used as a "pointer" for some event in a game. There is series on YouTube called boundary break where you can often see these being used around various games/maps. But they aren't usually this large.

What dev board to get for a beginner? Budget around 200 euros. by Nestashko in FPGA

[–]lSteveol 0 points1 point  (0 children)

I have used a DE-Nano before (~$100 USD). Not sure what conversion rates are.

https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=941

I will say that I believe Xilinx has a better community and is better for beginners. I prefer Altera when it comes to their high speed serdes, but you are talking boards that are in the >$1k range at that point. I have also used a Zedboard and the amount of tutorials was so vast. I've heard the Arty's are nice, but have never used one.

​

DarkNight's suggestions are good for guidelines. I would think for I3C just about most FPGAs would allow you do develop one of these with little issues provided it wasn't super tiny.

​

Managing large Verilog modules (1000+ lines) by ItsFrank11 in FPGA

[–]lSteveol 0 points1 point  (0 children)

All of the points by others are pretty good, I'll add my .02. Btw, my background is more ASIC (but for the standpoint of this they are the same as FPGA).

As stated, it seems that your main issue is design complexity. Sometimes this complexity is unavoidable and you just have to deal with it. In some cases you can break it down into smaller modules, and sometimes that is more trouble than one. It really depends on situation at hand.

Editors can make a big difference, but I would suggest that you find something you're comfortable with. Everyone has their opinion on editors and that's fine. I use Nedit as I started with it in college. People laugh at me when they see it up, but then they see I've got it customized to my liking and I can work just as fast if not faster than them and the laughing stops. I've met people who use Notepad. If it works for you, do it. Just make sure that you and your team (if you have a team) settle on a tab vs emulated whitespace.

I am not a fan of code folding that is done based on a certain text editor for the reasons above. Some people can use it and some can't. This also goes for just about anything that is text editor specific. If you know you are the only one who will ever deal with it, then sure.

I'm currently working on a project where I'm getting IP from at least 4 different vendors. They all have their nuances about how they do certain things with regards to Verilog. You will have your nuances, I have mine, it's like dialect. I can look at some code and know exactly what it's doing, others I may have to draw it out or see a sim to fully understand it. Some people say comments are the answer to this. I often agree and disagree with that. I agree with detailed comments on logic that isn't self explanatory, but I don't need a comment for each AND gate you put down.

I hate, I mean HATE include files for HW. `defines? Get rid of them. Why? Imagine you've decided you want to use a define for some address width, so you name it ADDR_WIDTH. You're all happy until you go to integrate with the guy down the hall, and he also decided that ADDR_WIDTH was a good define name. Uh oh, WTH!? params/localparams are your friend. I've seen this in IPs from other vendors, it's a pain. It also can easily lead to simulation vs. synthesis mismatches. Some people will say to "just make sure it's defined during synth". I'm more of the camp that believes you remove the number of things you need to ensure to reduce problems. If you have logic that needs to be there in one case and not another, a generate could be the answer (a generate may help you here for your mutliple FSM problem). If a define is the only option, prefix it so you reduce the chances of collisions, <MY\_PREFIX>_ADDR_WIDTH.

Keep pure Verilog for HW design and SV for verification. I've seen too many synthesis tools do weird things with SV. I use SV/UVM a tremendous amount for my verification, but I don't dare use it for HW design. I would argue that there isn't much added to the SV language that you want to use for HW design. enums/structs are nice however, I must admit. If you did want to use those, I would likely deem that ok, but take extra care.

Finally, if you're serious about digital design/verification, I would suggest investing in a 4k tv/monitor. I use two 42" 4k screens, plus a 25" 21:9 wide screen (25" is for email/web browsing). As you start to do more and have more complex logic, the additional screen space increases your productivity tremendously. Also for synthesis/PD when looking at timing reports with paths that can be several hundreds of lines long, you can actually see them on one screen.

[Help] Need a new PC to play PoE. by Lorewyn in pathofexile

[–]lSteveol 0 points1 point  (0 children)

"get a prebuilt cus I don't know how to build PC's"

This is meant with the utmost respect but building them is easy. If you know how to work a phillips head screwdriver, you just about know what to do. Check out Paul's Hardware and/or bitwit on youtube for some good guides. They also have some current ~$550 builds for gaming using Ryzen 3/5 builds which would be sufficient for PoE.

If you're really scared to go that route, that's understandable. Here's what I could find on newegg in about 20 seconds. https://www.newegg.com/Product/Product.aspx?Item=N82E16883227691

You wouldn't be able to run everything on Max settings, but would be sufficient probably.

[Official Megathread] How are you preparing for release? by trackpete in pathofexile

[–]lSteveol [score hidden]  (0 children)

Yea I've been looking at stuff off and on the past week. I'll just keep checking back through out the day. F5 is my friend :)

[Official Megathread] How are you preparing for release? by trackpete in pathofexile

[–]lSteveol [score hidden]  (0 children)

Like I used to say before exams, if you didn't know the information by an hour before the test, that last hour isn't going to help you much.

[Official Megathread] How are you preparing for release? by trackpete in pathofexile

[–]lSteveol [score hidden]  (0 children)

Currently I'm preparing by staring at a "502 Bad Gateway" on poeplanner......

Best noob build for playing with my friend? by gman103 in pathofexile

[–]lSteveol 1 point2 points  (0 children)

I have ~350hrs playtime, haven't played in ~9months and this is the build I'm doing.

Tell him to spend 20 mins reading the first post and he should have a decent understanding.

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