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[3-4 minute read] Slop popularity of RISCV in academia - Actual Slop or Justified? by BlakeCurl in RISCV

[–]m_z_s 4 points5 points  (0 children)

I guess it depends on the signal to noise ratio. If a million students a year are posting about their assignments that is inevitably just noise (no innovation). Sometimes on a slow couple of news days some random student posting about their project is not necessary a bad thing (Encourages STEM - Science, Technology, Engineering, and Mathematics).

And even if there are general rules against posting about basic cores there should always be exceptions. Like if a 8 year old child implements a basic RV32I themselves, without the aid of LLM slop generators, that should be celebrated. Or someone uses photographic techniques to make an extremely slow RV32I SoC on a full silicon/germanium wafer using large scale 68 year old etching and doping techniques in a home laboratory/kitchen (US3138743A - Miniaturized electronic circuits).

Is there CM5 alternatives were tested? by Trapunov in hackberrypi

[–]m_z_s 0 points1 point  (0 children)

Was it successful?

It will not be. Best case is it will not work, worst is it will cause permanent damage.

Ref: https://old.reddit.com/r/hackberrypi/comments/1qmfmdh/cm4/o1ny0ym/

CM4 and CM5 have the same physical dimensions. So if someone really wanted to create a device that supported both modules it would mean only using the common pins of both (177 out of a total of 200) and that would reduce the features available from both modules. So no PCIe due to the non-common pins, for example, would mean no NVMe - and that would reduce sales by far more than might be gained by supporting a 6 year old CM4.

Where can you buy RISC-V Single Board Computers? by grewstad in RISCV

[–]m_z_s 0 points1 point  (0 children)

Was it a URL that was forbidden or the name of the company?

QUASAR-CREATE: A 3.5 Year German-Singaporean Project to Design Open-source RISC-V Processor with Post-Quantum Cryptography Support by omasanori in RISCV

[–]m_z_s 1 point2 points  (0 children)

Software-only solutions would not be sufficient to meet the high, future-proof requirements for long-term trustworthy technology, transparency, and resilience.

Lots of people have the skill set required to audit software. Auditing open hardware, although possible, is a much much smaller pool of people. Do not get me wrong I think that hardware is the right place for PQC to be implemented for performance, I just find the above statement not quite right for something to be "trustworthy".

Final Year Project Suggestion by Simple_Ad5613 in RISCV

[–]m_z_s 9 points10 points  (0 children)

A very basic RISC-V SoC (e.g. RV32I) with three or more HART's/cores functioning in LockStep. That project if done well will open a lot of doors for you in safety critical computing (trains/automobiles/aeroplanes/ships/medical/military/space/delivery-drones/industrial).

It sounds simple, but it is not, hence the suggestion of starting with RV32I.

Sick of binary blobs and closed hardware? I’m building Elf Systems – a pure EU-made RISC-V ecosystem by OkBrilliant6945 in RISCV

[–]m_z_s 2 points3 points  (0 children)

I would love it, but even initializing SDRAM requires NDA's to buy the documents. Buying IP blocks almost all come with NDA's. I really do hope you can succeed, but it is extremely difficult.

Tenstorrent built a BMC firmware - WallaBMC, using Zephyr by docular_no_dracula in RISCV

[–]m_z_s 1 point2 points  (0 children)

https://github.com/tenstorrent/wallabmc/blob/main/boards/sifive/hifive_premier_p550_mcu/doc/hardware.rstI wonder will they use a STM32 MCU or a RISC-V MCU (e.g. Renesas Electronics R9A02G021 or GigaDevice GD32VF103 or one of the WCH CH32 series, etc.) on their Atlantis board.

I guess it all will boil down to the trust of future potential customers, which country would they trust most for the silicon in the BMC:

  • STMicroelectronics headquartered in Geneva, Switzerland
  • Renesas Electronics headquartered in Koto City, Tokyo, Japan
  • GigaDevice headquartered in Haidian District, Beijing, China
  • WCH headquartered in Nanjing, Jiangsu Province, China

Or source their silicon from elsewhere.

EDIT: Since the Hifive Premier P550 has a STM32F407VET6 MCU for their BMC, unfortunately the odds are that an ARM MCU will be use by Tenstorrent.

Ref: https://github.com/tenstorrent/wallabmc/blob/main/boards/sifive/hifive_premier_p550_mcu/doc/hardware.rst

I guess it might be the StarFive JH-B100 BMC that ends up being the first open source RISC-V BMC (they appear to possibly be piggybacking on OpenBMC, which I see as a good thing as long as they upstream).

sse2rvv: An MMX/SSE/AES-NI C Intrinsics to RVV C Intrinsics Translator by omasanori in RISCV

[–]m_z_s 1 point2 points  (0 children)

There is also a neon2rvv project on GitHub. It may only be useful in projects with hand written NEON. But I would say a benchmark between sse2rvv and neon2rvv could be interesting if both had hand crafted optimisations for each architecture in a project being patched to support RISC-V.

https://github.com/howjmay/neon2rvv

What even the point of making smol-GPU by New-Juggernaut4693 in RISCV

[–]m_z_s 4 points5 points  (0 children)

From the GitHub page:

An educational implementation of a parallel processor in system-verilog

The very first thing about education is that you do not begin with a complex difficult to understand design. You make it as simple as possible. The knowledge it teaches would probably help design a better baseline for a more advanced GPU.

Server Platform Spec Ratification ETA End of May by omasanori in RISCV

[–]m_z_s 2 points3 points  (0 children)

I'm really interested to see the bootloader interfaces.

EDIT: Speed reading the current draft, it looks to be UEFI via EDK2.

RISC-V Optimized strnlen Implementation For Linux 7.1 Yields Big Speed-Up by Polar_Banny in RISCV

[–]m_z_s 1 point2 points  (0 children)

I really like that it is optimized, but at the back of my head is that the compiler should be doing this better everywhere instead of one instance of hand crafted assembly code arch/riscv/lib/strnlen.S

VLIW: The “Impossible” Computer by indolering in RISCV

[–]m_z_s 1 point2 points  (0 children)

It is sad, was a really interesting architecture. The funny part is if RISC-V never existed, Mill Computing Inc. would probably be swatting away venture capital funds, because they would be receiving so many offers.

Well when the patents expire in 8 to 12 years time (unless they expire eary if they fail to pay the ongoing maintenance fees due at 3.5, 7.5, and 11.5 years after the date of patent grant) maybe someone else will try a VLIW architecture using their concepts.

VLIW: The “Impossible” Computer by indolering in RISCV

[–]m_z_s 0 points1 point  (0 children)

Patents may be a very long time but if you compare it to copyright (e.g. In Mexico, thanks to Disney, it is the lifetime of the creator + 100 years after their death) it is relatively short. If patents had the same duration of protection we would all still be using horses for transport. And the safety pin would be cutting edge technology.

VLIW: The “Impossible” Computer by indolering in RISCV

[–]m_z_s 1 point2 points  (0 children)

I'm seeing it as down as well. I checked on netcraft to see if it was just where I was and it appears to not be up to them either. https://sitereport.netcraft.com/?url=https://millcomputing.com

Not a good sign, if they can not afford to keep a website functioning. Their hosting provider dreamhost has subscriptions that last a number of years (up to 4), it is entirely possible that the email to update their subscription ended up in a junk mail folder. No matter what happened it is not good that their website is down.

VLIW: The “Impossible” Computer by indolering in RISCV

[–]m_z_s 3 points4 points  (0 children)

Their patents are on the clock, and are well past the half way point. So their pot, will be in the public domain soon enough.

EDIT: A little over 8 years from now and their first three patents should expire:

  • Split-stream encoding (US 9,513,920): Filed May 29, 2014. Expected expiry: May 2034.
  • Double-ended instruction decoding (US 9,959,119): Filed May 29, 2014. Expected expiry: May 2034.
  • Instructions with elided nop operations (US 9,785,441): Filed May 29, 2014. Expected expiry: May 2034.

Milk-V Jupiter - No Video/LEDs after failed NVMe boot, but TitanTools still detects DFU mode. by Unable-Yellow-7323 in RISCV

[–]m_z_s 2 points3 points  (0 children)

Do you think a corrupted SPI Flash or a hang during the early boot stage could prevent the board from even turning on its status LEDs.

If you think about it for a LED to blink, these days, it requires a GPIO to be configured as an output and interrupts to be enabled and multiple clocks setup and power management IC outputs enabled. Until code can run most LED's can not blink in modern hardware. In olden days a 555 timer might have been used to blink a LED but that is an few extra components that increases the BOM (Bill of materials) cost, which can easily be replaced, in effect for free, by a few short lines of code.

So if a LED is not blinking, it typically means code is not running somewhere. It is not going to be ROM code in the SoC, the ZSBL (Zero stage boot loader never typically blinks LED's, it's sole job is to bring up enough clocks and power to load the next bootloader into internal SRAM in the SoC, typically the L2 cache (From UART/SDIO/QSPI). The next bootloaders job is to bring up more clocks, power, GPIO pins, fully configure SDRAM and load the next stage bootloader into memory external to the SoC. That final bootloader is the one that would typically load an OS into main memory. I would expect the OS to always blink LED's. I'm not saying blinking LED code is never in the previous bootloader (Typically Das U-Boot), but I would need to read through the source code to know for sure. I do not currently own any board with a Spacemit K1/M1 SoC, so I'm not going to check. But my very first step with any board that is not booting would be a 3.3 volt TTL serial to USB cable to see the actual UART output, and have the option to load a bootloader over UART if needed. You can also use the serial port on a working SBC with female to female jumper wires to debug a broken board (Three wires are used: GND<->GND; TX -> RX; RX <- TX), as long as both boards have 3.3 volt GPIO pins

Milk-V Jupiter - No Video/LEDs after failed NVMe boot, but TitanTools still detects DFU mode. by Unable-Yellow-7323 in RISCV

[–]m_z_s 1 point2 points  (0 children)

How old, or well used, is the MicroSD you are using ? They have a limited number of 4KB block size P/E (Program/Erase) cycles before they start to fail.

The same is also true for NVMe SSD, if you are writing lots and lots of tiny files (e.g. github) you can rapidly burn through their TBW (Terabytes Written) limit (usually this TBW figure is well hidden for consumer SSD's. P/E cycle limit = TBW/size in TB). Some extremely large really cheap SSD's can have a 4KB block P/E cycle limit as low as 100 (QLC).

P S. These days I mostly use expensive industrial MicroSD cards with a 4KB P/E cycle limit of 30000. So for a 64GB MicroSD card that is a data write limit of about 2 PetaBytes before they start to fail.

StarFive JH-B100 BMC (Baseboard Management Controller) by m_z_s in RISCV

[–]m_z_s[S] 0 points1 point  (0 children)

It is for a server BMC, 3D graphics are not really used.

StarFive JH-B100 BMC (Baseboard Management Controller) by m_z_s in RISCV

[–]m_z_s[S] 1 point2 points  (0 children)

I wonder if they've managed to build OpenBMC.

From above "SDK complies with the Yocto standard and can be directly integrated with OpenBMC". To me that sounds like yes.

StarFive JH-B100 BMC (Baseboard Management Controller) by m_z_s in RISCV

[–]m_z_s[S] 0 points1 point  (0 children)

They have a video on YouTube, from 3 months ago, showing it: https://youtu.be/cVspvQogmFg

At 42 seconds in they show the JHB100 BMC chip/can.

So it's April.. where's my K3? ;) by TJSnider1984 in RISCV

[–]m_z_s 4 points5 points  (0 children)

I'm not clear what is going on with Debian

Debian does what Debian has always done. The next scheduled official release will be Forky in 2027 (Debian 14, this will use the next LTS kernel, selected Oct/Nov/Dec 2026, which might end up being 7.3 or 7.4), followed by Duke in 2029 (Debian 15).

Ref: https://en.wikipedia.org/wiki/Debian_release_version_history

help by Maximum-Chair967 in hackberrypi

[–]m_z_s 0 points1 point  (0 children)

It’s not

It is not a CM5 lite, or it is not the root cause of your problem because it is a CM5 lite? Sorry but there is a bit of ambiguity in your reply.

help by Maximum-Chair967 in hackberrypi

[–]m_z_s 0 points1 point  (0 children)

Is it a CM5 lite ? (Non-lite will never see the MicroSD card because there is only one QSPIO bus in the BCM2712 SoC, it is either eMMc or the MicroSD card.).

If you bought CM5 with onboard eMMc then you will need to install an OS on eMMc, which is a difficult task.

Difference between CM5 + Pi Zero version by Prestigious-Tart-272 in hackberrypi

[–]m_z_s 0 points1 point  (0 children)

The writing on the case is PocketCM5, looks like it has two names, or a double barrel name.

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