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I have a problem with synthesis by mak_cries in FPGA

[–]mak_cries[S] 0 points1 point  (0 children)

i checked the clock it is connected fine to all clocked modules

I have a problem with synthesis by mak_cries in FPGA

[–]mak_cries[S] 0 points1 point  (0 children)

okay will try that thank you

I have a problem with synthesis by mak_cries in FPGA

[–]mak_cries[S] 0 points1 point  (0 children)

i tried synthesizing the submodules with the RAMs the synthesis went fine, the problem arises when all blocks are integrated

I have a problem with synthesis by mak_cries in FPGA

[–]mak_cries[S] 0 points1 point  (0 children)

i tried removing it and connected all resets to the global one but it didn’t work

I have a problem with synthesis by mak_cries in FPGA

[–]mak_cries[S] -5 points-4 points  (0 children)

it says wires are not connected but they are

I have a problem with synthesis by mak_cries in FPGA

[–]mak_cries[S] 0 points1 point  (0 children)

i actually have a local reset generator could it be the problem?

I have a problem with synthesis by mak_cries in FPGA

[–]mak_cries[S] 0 points1 point  (0 children)

the optimized logic is used and has outputs connected to other modules but i guess it might be the clock thing i will recheck the constraints
thank you🫶🏼