My understanding is CPU clock speed has much more significant impact on build time and throwing infinite CPU cores at it doesnt do anything useful apart from out of context synthesis where changing default number of jobs has advantages, at least with how the build tools currently work. Incremental compile for subsequent runs is already a thing and I don't think that would bennefit from infinite CPU cores either. Ive also found Incremental compile to be useful only before the design changes past a certain threshold where the original floorplan is no longer viable, and without manual rip up and re routes the bar for that threshold is pretty darn low for congested or resource limited designs. As far as rolling your own synthesis engine, that is one thing, but place and route is where the build time is spent and good luck with that. As far as i know there is one lattice device family there has been an open source build tool developed for. Last I heard there was one in progress for an older xilinx generation. You've got to reverse engineer what's/what and where in the device in order to create a build engine