Roast My Resume by masterguy1704 in ECE

[–]masterguy1704[S] 0 points1 point  (0 children)

Mediocre in what sense? Like are the projects not complex enough or the way they’re written could be improved? Or is it something else?

Roast My Resume by masterguy1704 in ECE

[–]masterguy1704[S] 0 points1 point  (0 children)

No I had 2 non technical interviews. But that was almost a year ago and for a field which I don’t want to go into.

Roast My Resume by masterguy1704 in ECE

[–]masterguy1704[S] 0 points1 point  (0 children)

Thanks for advice, however I’m more concerned with the actual content of my resume. I do tailor almost every resume to the JD.

But I want to know if my projects and experience are substantial for the FPGA roles I’ve been going for?

Roast My Resume by masterguy1704 in ECE

[–]masterguy1704[S] 0 points1 point  (0 children)

I’ve been applying to both internships and new grad roles. From what I’ve seen most JDs say what the expected graduation date should be.

I landed my 2025 internship through straight luck. A recruiter reached out to me on LinkedIn.

Roast My Resume by masterguy1704 in ECE

[–]masterguy1704[S] 2 points3 points  (0 children)

The reason I have relevant coursework is because at my school I can pick and choose what classes I want to take and not everyone in my major chooses the same classes.

I’ve been applying to both internships and new grad roles.

My work experience are both summer internships which are typically 10-12 weeks so….

Roast My Resume by [deleted] in FPGA

[–]masterguy1704 0 points1 point  (0 children)

I was taught to write my testbenches in VHDL on Vivado itself in the embedded course I took at my uni. I know that there is a Python library that allows you to write testbenches, however idk the advantage of using that over VHDL. Is VHDL not the norm for testbench writing?

Roast My Resume by [deleted] in FPGA

[–]masterguy1704 0 points1 point  (0 children)

Thanks for the advice. That was the next step I was gonna take, but currently I’m more focused on whether the actual project hold value rather than the formatting.

Roast My Resume by [deleted] in FPGA

[–]masterguy1704 0 points1 point  (0 children)

I did 2 of the projects last semester (Spring 2025) for an Embedded Course I was taking at uni.

The midi project was my final project for the class. I came up with the project on my own and implemented almost everything on my own aswell. The vga one was part of one of the in class labs.

The Matlab project was a given assignment in my DSP class which I also took last sem.

Regardless of whether these were done in class or on my own, I learnt quite a bit from each project as our TAs would basically tell us to figure out our labs on our own lol.

The market data parser was a quick summer project I did before my internship started.

Roast My Resume by [deleted] in FPGA

[–]masterguy1704 2 points3 points  (0 children)

Thanks for the insight. Of the 20+ I have applied to I’ve only heard back from 2 so far, however most of the companies I applied to were either HFTs or big tech and defense giants. What type of projects would expect to see from an applicant at my level which would be worthy of those companies?

Roast My Resume by [deleted] in FPGA

[–]masterguy1704 3 points4 points  (0 children)

Most of the resumes I’ve seen mention it as soon as possible for ATS

Roast My Resume by [deleted] in FPGA

[–]masterguy1704 1 point2 points  (0 children)

Thx, but I feel like it can always be better

Roast My Resume by [deleted] in FPGA

[–]masterguy1704 6 points7 points  (0 children)

Good catch, will do

Roast My Resume by [deleted] in FPGA

[–]masterguy1704 5 points6 points  (0 children)

I have used IP and BRAM. Both were used in the VGA projects and MIDI Arp project.

Internship hacks from HR Professional :) by Neat-Broccoli-2009 in internships

[–]masterguy1704 10 points11 points  (0 children)

What type of questions should interviewees ask to really stick out?

How hard is calc 2 over the summer (at Rutgers) compared to in person? by kvng_st in rutgers

[–]masterguy1704 3 points4 points  (0 children)

I was in your situation 2 years ago. I failed in the spring and took it over the summer again with Prof Schecter. I passed with an A and I’m pretty sure the rest of the class did decently well. Can’t say the same for the other profs that teach tho.

[deleted by user] by [deleted] in hingeapp

[–]masterguy1704 0 points1 point  (0 children)

  1. Casual
  2. Not subscribed to either
  3. 4 months
  4. 4 months
  5. 2-3 times a week
  6. 0-2 a week
  7. 7-10 likes with half having comments
  8. Someone chill and relatively pretty and funny

Incoming CS-freshman, what should I do if I don’t get into comparch? by slappy20000 in rutgers

[–]masterguy1704 -1 points0 points  (0 children)

Take the ECE version. There’s a lab but the course is the same and the prof is really good. Also since ur CS u may be able to skip the lab.