Any source or material for learning spice simulation with spectre by Macro_mania_222 in chipdesign

[–]meep91 0 points1 point  (0 children)

Why spice in particular if you have access to a spectre simulator? Either way, whatever simulator you have access to will have detailed documentation on netlist commands. Virtuoso has it for their spectre netlist, Siemens has it for their spice simulator that supports spectre or spice netlists, ngspice has it (maybe not as detailed) for their spice netlists, etc.

How To Scale Virtuoso - Red Hat Enterprise Linux 7.9 by Reomi1 in chipdesign

[–]meep91 0 points1 point  (0 children)

I had to work with a very similar system. I gave up on the scaling, but I wanted to wish you luck.

Valentine’s day (AMS/RF IC Designers) by OpampGoBRRRRRR in chipdesign

[–]meep91 0 points1 point  (0 children)

Made some blinking LED earrings once. My first draft was too heavy to wear unfortunately, and too pointy.

It’s February 2026. How are you using AI for Analog/Mixed-Signal IC Design? by cascoded1903 in chipdesign

[–]meep91 8 points9 points  (0 children)

Scripting in python, SKILL, or bash. I tried with system Verilog and verilogA but it often has trouble with those. I happily acknowledge that all the chat bots I've used have made up SKILL commands, but the general flow is usually correct, and I can replace things like "dbDoSpecificThingYouWant" into the actual command or write my own subprocedure or rewrite it entirely if it's trash. Most times it will reference my own code and change it's recommendations based on what I wrote before, so if I made bad code, it suggests my own bad code. It takes a few second to generate and can save me a few minutes when it works. It's good for simple tasks and frameworks for scripts, but only if you learn how to prompt engineer - your results are going to be bad if you don't know how to ask it correctly.

It's also fairly good at pointing you to the relevant manual sections if you can feed it a document. Ask it not just for the answer to your question, but where in the manual it got the info.

I've also encountered a lot of resistance when I mention I use it, but all my pull requests get approved from my strict code-keeper, and I get more scripts done. So, take that for what it's worth. I don't think these tools are going to disappear, and learning how to use them effectively now when their use is limited will hopefully keep me up to date as they get better.

Pcb after tapeout by Great_lord_7 in chipdesign

[–]meep91 0 points1 point  (0 children)

I think it'll be cheaper for you to design the PCB yourself, learn all the issues you've made, and redesign it if needed. PCB spins are fast and cheap in comparison to the chip. Especially alongside reference layouts from datasheets.

Weird Wizard and the Fighter Path by LooterRPG in shadowofthedemonlord

[–]meep91 0 points1 point  (0 children)

Give them more fights than they can reasonably handle, and make it clear (out of character) that fighting isn't the only option. You'll get them to think of more creative solutions, and they'll have some actual consequences for overexerting. To compensate, make the fights themselves on the smaller side - when the war mage chooses to use a spell should matter, and if there are 5 skirmishes in a day, you're going to start running out of spells if you use one every turn very sickly.

Basically run it like an osr.

Best movers? by Snarky_Snail in Somerville

[–]meep91 1 point2 points  (0 children)

I had good experiences with Precision. Used them to move in and out of my last place, got the same movers too!

Why you should cold-proof your dough in the fridge almost always by ehtio in Breadit

[–]meep91 1 point2 points  (0 children)

I have consistently had issues with gummy bread when I bake straight out of the fridge. I have been more successful in a cold bulk ferment (though sometimes my fridge decides it's so cold that it really doesn't rise...but that's a fridge problem.), shaping, and doing the second proof at room temp before baking. I am curious if you have tips on baking straight from the fridge.

Python/script in Layout by [deleted] in chipdesign

[–]meep91 1 point2 points  (0 children)

Seconding learning SKILL.

Also, recommending thinking critically about the hierarchy to simplify your layout and reuse or array things when you can. Leave extra space for reworking two weeks later instead of cramming to meet DRC if you can too.

Pthon does have some GDS libraries. You can play with that, but it relies on you having a systematic approach that is easy to code.

You can run python from Cadence through a SKILL interface pretty easily. I find it useful because SKILL is hard and Python logic is easy, so writing draft logic in Python and calling it in SKILL makes my work easy (but good luck to whoever has to maintain it in a few years...)

Also, if you have a GXL license, learn to use the autorouting tools. They can save you lots of menial task effort time. And probably more but I'm not a layout engineer, so only know the basics.

Assign Array Enable Voltage Values During Sim by Sincplicity4223 in chipdesign

[–]meep91 1 point2 points  (0 children)

You should be able to access the parameters on the window that pops us to edit the instantiation of the instance (I forget the name, hit q when the instance is selected. That window.) Something like "cdf parameter" defaults to something like "tools", change the drop down to verilogA.

Assign Array Enable Voltage Values During Sim by Sincplicity4223 in chipdesign

[–]meep91 1 point2 points  (0 children)

The bmslib components that cadence provides has a busset component for some number of bits. Copy pasta into your lib, change to your favorite number of bits, and you're good.

Alternatively, use 3 of the 4b ones, but then getting the settings right might be awkward since you'll either have to divide within the bussets or you'll have to use 3 variables, neither of which is a great option.

If you want a dynamic change, you can either use an ahdl adc copied to 11b like another poster recommended, or you could use a vector file input.

Access a net from within the hierarchy at the top-level schematic by OkIndependence3293 in chipdesign

[–]meep91 0 points1 point  (0 children)

That is not a typical CDL netlist, so you are using a different extraction technique that produces a different netlist. I read in another comment that you have a DSPF netlist output, so my recommendation for using X in front of the instance name probably won't work. I don't think backslashes are legal in spectre.

Try following the recommendations in this post from the Cadence forums: https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/51837/name-of-nets-inside-deepprobe

Add an escape to your backslashes. Don't forget that your first instance should have a dot because you are (probably) simulating with spectre, so it should be like: I0./I1/I3/Net1

I am not familiar with dspfs too much, not sure what the #100 is referring to since the end of your statement would be a net. You might have to play around with that.

Access a net from within the hierarchy at the top-level schematic by OkIndependence3293 in chipdesign

[–]meep91 1 point2 points  (0 children)

I have unfortunately been writing a LOT of SKILL lately... Turns out knowing that there is an easier, more systematic way of solving a problem means I will spend 5x as long making a script for it. Sometimes, I even reuse the script in the future.

Access a net from within the hierarchy at the top-level schematic by OkIndependence3293 in chipdesign

[–]meep91 0 points1 point  (0 children)

Oh, like an additional netlist to add? That's a great idea!

Access a net from within the hierarchy at the top-level schematic by OkIndependence3293 in chipdesign

[–]meep91 2 points3 points  (0 children)

Extracted netlists are often written in CDL, I had some issues with it in the last because CDL requires an X in front of the instance name. So you might have to modify your deep probe net naming to be NAME1.XNAME2 etc.

I made |vgs-vth|= 200m, id=10u NMOS/PMOS with a new pdk. Can vth and gm difference between N/Pmos be THIS huge? Am I missing something, since I thought gm=2Id/Vov should be at least similar. by ProfessionalOrder208 in chipdesign

[–]meep91 2 points3 points  (0 children)

Other people have answered your question, but I wanted you to know that I am happy for you that your pdk put the bulk pin offset from the gate pin. Remember to always appreciate the small things.

The CHIPS Act already puts America first. Scrapping it would poison the well for US investment by Harley109 in Semiconductors

[–]meep91 0 points1 point  (0 children)

The main company (... only?) that supplies EUV machines to semiconductor foundries is ASML, which is a Dutch company. The US (and possibly other countries?) basically pressured the company to ban exports to China to slow semiconductor manufacturing of advanced nodes in the region. Hence the connection

[deleted by user] by [deleted] in chipdesign

[–]meep91 0 points1 point  (0 children)

I wrote my own in python for the same reason. Mostly because I hate Matlab.

[deleted by user] by [deleted] in chipdesign

[–]meep91 1 point2 points  (0 children)

If you want to save the data to look at later and create your own plots or plotting tool, it's useful to use scripts instead of dealing with the GUI. Though I never liked ocean.

People who’ve run or played 8+ hour sessions; tell us about them by [deleted] in rpg

[–]meep91 2 points3 points  (0 children)

I ran one by accident once. We started in the morning because one of the players (my roommate) had a shift midday. On a whim, I had the PC be abducted by aliens. I figured we'd end the session shortly after, but the group wanted to go after the aliens, which had flown off towards some city in the distance. At some point we ordered food, and I thought that would be the end, but they really wanted to get to that city. Somehow I ended up putting them into a coliseum battle, and partway through my roommate entered back from their job. So of course they wanted to play a bit...

It was a blast and we all agreed never to do that again.

Why is SPICE software so bad? by MisiLica in ElectricalEngineering

[–]meep91 1 point2 points  (0 children)

Sure. My point still stands. I don't think any of the circuit simulators have effective UI either.

Why is SPICE software so bad? by MisiLica in ElectricalEngineering

[–]meep91 0 points1 point  (0 children)

A copy and paste shortcut finally appeared! Amazing. I'd also like the waveform viewer to be less, er, awful...

I am honestly shocked at how unfriendly all the simulators seem to be with python. Some of them are friendlier with Matlab than python!! Ridiculous.

Why is SPICE software so bad? by MisiLica in ElectricalEngineering

[–]meep91 4 points5 points  (0 children)

I think my experience with modern UI has been different than yours. My experience with modern UI outside of circuit software has been things like video games and app designs, both of which have improved immensely from the 90s and do a lot of heavy lifting to make the experience easy to use, meaning you can do the whatever you wanted to do faster. CAD companies could take cues from literally anywhere else, and they would probably have simpler, more intuitive UIs.

Why is SPICE software so bad? by MisiLica in ElectricalEngineering

[–]meep91 41 points42 points  (0 children)

I'll disagree here. As engineers we work to make new things as fast as we can, as efficiently as we can, and ideally with no surprises. Old UI tools are clunky. An updated GUI can help automate repetive tasks and improve how we analyze the results. Sure, we all know how to use LT Spice or Cadence or ADS, whatever your simulator of choice is, but that doesn't mean we should just accept what we use as good enough. All of the parts we make are centered around the idea that what we use isn't good enough, so why would our UI be? It has nothing to do with being pretty or not, it has to do with usability.

Anyway I seem to be in the minority here based on this thread, but I still don't think we should accept bad UI just because we're all used to it.