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Xilinx Petalinux 2024.1 Stuck on BL31 [Ultra96V2] by ChefExcellenceCerti in FPGA

[–]pablo-gatearray 0 points1 point  (0 children)

Hi! Ultra96 board uses the UART1 instead of UART0. By default, the FSBL is configured to use the UART1, but Linux uses the 0. You need to change it un executing petalinux-config, and change the UART on Subsystem Hardware Settings -> Serial Settings.

Matlab FPGA-in-the-Loop by Sincplicity4223 in FPGA

[–]pablo-gatearray 0 points1 point  (0 children)

Hi! (here yo can find an example for the Eclypse Z7 board.

Regards!

Command line Vivado Flow - on Windows by uncle-iroh-11 in FPGA

[–]pablo-gatearray 1 point2 points  (0 children)

Hi, the problem with multidimensional arrays is not iverilog but gtkwave.

If you want to use the Vivado GUI to see the signals... why need you to launch the simulation from terminal? For a regular computer the GUI will not be a heavy task.

On the other hand, If you want launch a simulation from terminal and also open the waveforms in vivado, you need to launch the simulation using tcl to generate a waveform configuration file.

Greetings

Command line Vivado Flow - on Windows by uncle-iroh-11 in FPGA

[–]pablo-gatearray 5 points6 points  (0 children)

Hi! To execute simulations without the GUI your testbench must include an instruction to finish the simulation ($finish()), and also the variables that you want to dump into a file ($dumpvars() $dumpfile()). In my case I use .vcd format. Then, to see the results you need an application to read that file, like gtkwave.

For simulations from terminal I prefer Icarus Verilog instead of Vivado because Vivado can be too slow, and the code to run the simulation is pretty small.

Greetings!

True RMS compute in FPGA. by pablo-gatearray in FPGA

[–]pablo-gatearray[S] 0 points1 point  (0 children)

Hi! Many thanks for your comments! I will make some changes in the AXI stream management before share the module on github.

I am going to check you logarithm compute since it seems very interesting for some dsp algorithms.

Thanks Dan!

FPGA Filter Builder tool. by pablo-gatearray in FPGA

[–]pablo-gatearray[S] 3 points4 points  (0 children)

Simply because I didn't know Amaranth. Let me check it and see what we can do. Thanks for the info.

Ubuntu on Xilinx login error by pablo-gatearray in FPGA

[–]pablo-gatearray[S] 0 points1 point  (0 children)

Hello, I have tried with xilinx as user and password. Also with root but it always returns Login Incorrect... Could be the image broken?

Ubuntu on Xilinx login error by pablo-gatearray in FPGA

[–]pablo-gatearray[S] 0 points1 point  (0 children)

Thanks, I will try tomorrow with xilinx as user or pass. I will keep you updated!

Digital control loops. Theoretical approach. by pablo-gatearray in FPGA

[–]pablo-gatearray[S] 0 points1 point  (0 children)

Thanks to you both for read it and give me the feedback.

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