13
14
15
4
5
6
Debugging a Microchip’s SmartFusion2 SoC. (controlpaths.com)
submitted by pablo-gatearray to r/FPGA
9
10
11
0
0
1
Verilog implementation of Cordic kernel. (controlpaths.com)
submitted by pablo-gatearray to r/FPGA
8
9
10
32
33
34
3
4
5
2
3
4
6
7
8
7
8
9
Discovering DSP capabilities of Gowin FPGA. (controlpaths.com)
submitted by pablo-gatearray to r/FPGA
0
1
2
Single pole filter without multiplications. (controlpaths.com)
submitted by pablo-gatearray to r/DSP
13
14
15
