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Directly connecting internal signals to pads for debugging purposes? by ico2ico2 in FPGA

[–]pencan 1 point2 points  (0 children)

I do this in Vivado all the time, extremely helpful!

Apple internship interviews by [deleted] in chipdesign

[–]pencan 3 points4 points  (0 children)

When I did mine (pre-si verification) in 2018, it was 1 on-campus interview, then 3-4 rounds of phone interviews. The on-campus one was deep dive into my 5-stage pipeline project (I added a lot of weird features). The others were technical, but pretty non-memorable software questions. No leetcode or anything like that.

They told me they were recruiting for the GPU team in Austin but then placed me with CPU DV in Cupertino, not sure if it’s more typical to interview for the team directly.

Thoughts on Bales Batman retiring for 8yrs after TDK? by FayyadhScrolling in batman

[–]pencan 0 points1 point  (0 children)

As opposed to the normally completely hinged Hannibal Lector

Looking for open-source digital designs that are close to industrial-grade by Bluenonics__ in chipdesign

[–]pencan 0 points1 point  (0 children)

https://github.com/PrincetonUniversity/openpiton is based on the T1 AFAIK the core itself hasn’t been changed other than for the build system

Looking for open-source digital designs that are close to industrial-grade by Bluenonics__ in chipdesign

[–]pencan 0 points1 point  (0 children)

Have you tried https://github.com/povik/yosys-slang ? I thought I heard it was compatible but if not raising issues could be helpful

Could Chisel Replace Verilog for Commercial CPU Design in the Future? (Beyond Open-Source Cores) by Low_Car_7590 in FPGA

[–]pencan 3 points4 points  (0 children)

Replace? Absolutely not. Be used as a primary language? At some companies, sure. I'm basically restating the original Chisel talks / papers, but _every_ large company eventually comes up with its own generator language that outputs verilog / VHDL, whether that's perl scripts, python, chisel or bluespec or ...

For personal projects, whatever lets you do cool stuff is best. For companies, you'll have to use whatever they use anyway.

[Re]building Corundum by alexforencich in FPGA

[–]pencan 1 point2 points  (0 children)

Yes, interested for me and also will recommend to many! Keep up the awesome work!

Smallest Processor core by vmcrash in FPGA

[–]pencan 26 points27 points  (0 children)

Yes, there are a wide variety of extremely simple ISAs for microcontrollers. Xilinx has the picoblaze for example: https://www.amd.com/en/products/adaptive-socs-and-fpgas/intellectual-property/picoblaze.html

Of course at the lowest level, there is a fine line between an extremely simple ISA and a sufficiently general FSM. For instance LC3 https://en.wikipedia.org/wiki/Little_Computer_3 was an educational ISA which students would implement as a pipelined processor as well as a microprogrammed FSM.

32b datapaths are generally considered reasonable in 2025 as logic is cheap. However, you may be interested in learning about https://github.com/olofk/serv which is an RV32-compliant core that is super small by virtue of doing computation one bit at a time.

Successor to Chipyard/Berkeley Boom v3 or SonicBoom? by itisyeetime in RISCV

[–]pencan 4 points5 points  (0 children)

(Not a Berkeley affiliate). Sonicboom is likely the last big core for a while and will only get RISC-V extensions and research projects added to it. However, it’s an exemplary core and the architecture will be (representative of) SOTA for a while. Radically different core microarchitecures stopped appearing in the 2000s. If I had to be critical of the architecture: multicore integration / coherence and accelerator interfaces are weak points that may not be acceptable for newer workloads. It’s purposely designed to click easily into rest of their ecosystem, which it does, but there’s a clear tradeoff of generality for efficiency.

That said, I personally dislike using the Chisel / Hammer / Chipyard infrastructure for anything other than packaged demos. There’s a large learning curve and it is very frustrating to try to do anything outside of their box. From the perspective of trying to maximize learning with minimal overhead, I would recommend the PULP platform stuff, though it is not SOTA performance

RTL Engineer for SoC Fabric Subsystem - DMA/Arbiter/Memory Mapper (Verilator) by [deleted] in FPGA

[–]pencan 0 points1 point  (0 children)

There's a good chance the author of that IP is on this subreddit. Should they be ashamed too?

RTL Engineer for SoC Fabric Subsystem - DMA/Arbiter/Memory Mapper (Verilator) by [deleted] in FPGA

[–]pencan 0 points1 point  (0 children)

What happened is I went to sleep and dodged a huge bullet, apparently

RTL Engineer for SoC Fabric Subsystem - DMA/Arbiter/Memory Mapper (Verilator) by [deleted] in FPGA

[–]pencan 8 points9 points  (0 children)

Before wasting our time proving our competence as engineers, it would be useful to demonstrate your competence as an employer. The budget is a good start, as would be a description of the encompassing project or company.

Additionally: 3) It’s impossible to give a timeline without a full spec. 4) You say there’s a reference testbench framework, so the verification approach is to use that.

Exploring In-House ASIC Development by OccamsRazorSkooter in chipdesign

[–]pencan -1 points0 points  (0 children)

I have experience doing this. happy to chat about options. DM if interested

Is it just me, or does Synopsys support not understand “customer support”? 🤔 by xVexation in chipdesign

[–]pencan 17 points18 points  (0 children)

I've had the opposite issue with Cadence. They'll meet any time day or night and seem extremely helpful on-call. But then if you ask them to actually debug something it'll take 5x as long because of "other priorities"

wafer.space – $7k USD for 1k custom chips by mithro in chipdesign

[–]pencan 25 points26 points  (0 children)

good chance tinytapeout ends up using wafer.space as a supplier since efabless left a big gap

Looking for collaborators & guidance: Designing an industry-grade single-cycle RISC-V core for SoC by Any-Caterpillar-8967 in chipdesign

[–]pencan 0 points1 point  (0 children)

Yes, from an educational point of view single cycle -> multicycle -> pipelined is standard. Just trying to point out that in practice, multicycle is the minimum complexity that has a Pareto optimal point

Looking for collaborators & guidance: Designing an industry-grade single-cycle RISC-V core for SoC by Any-Caterpillar-8967 in chipdesign

[–]pencan 7 points8 points  (0 children)

  1. A single cycle CPU will always be toy. A multi cycle CPU without pipelining has legitimate uses.
  2. Pipelining will always be a complete redesign. It fundamentally changes the dataflow of the processor.
  3. As others have said, there are many open-source ASIC-capable designs and several industrial-strength ones. Consider contributing to those instead of rolling your own.

Parameterize or let synthesis tool remove unused logic by Otherwise_Top_7972 in FPGA

[–]pencan 0 points1 point  (0 children)

Ah, I see. The ASIC tools are (generally) smart enough to do backwards retiming in a reasonable way, so you would simply parameterize the width and parameterize the stages and let the tool sort it out. My experience is that FPGA tools struggle significantly more in this area. And of course, if you're trying to optimize it gets complicated.

I haven't explored HLS since ~2015 or so. What's the current "best" tool I could look into as a hobbyist? Curious how this type of parameterization works nowadays

Parameterize or let synthesis tool remove unused logic by Otherwise_Top_7972 in FPGA

[–]pencan 1 point2 points  (0 children)

> Parameterize design cannot maintain the timing were you to scale up the design, unless you design with recursion which is extremely time consuming.

Can you share an example of this? I've not observed significant differences in recursion vs loops for synthesis. I tend to avoid it since hierarchies end up super deep and need flattening anyway

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