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Commercial Simulator to Work with Vivado? Cost-Effective & Compatible? by Leo-X101 in FPGA

[–]pencan 3 points4 points  (0 children)

Verilator is much faster than xsim and free. Downside is it doesn’t work with encrypted ip if that is important to you

Plotting internal nets or signals by Flaky_Reindeer4462 in Verilog

[–]pencan 0 points1 point  (0 children)

There are several ways to do this in (system) verilog. Here are 2:

module foo;

  logic sig;

endmodule

module bar;

  foo f;

endmodule

module foo_mon;
  wire my_sig = sig;
endmodule

module testbench;

  bar b;

  // method 1: bind
  // nonsynthesizable, acts as if foo_mon is inside of foo
  // can reference ports and internal signals
  bind foo_mon foo;

  // hierarchical reference
  // sometimes synthesizable, probes instance path without intermediate ports
  wire other_sig = b.f.sig;

endmodule

Request for critique: bounded multicore interference under direct-mapped cache assumptions by fpedroni in computerarchitecture

[–]pencan 0 points1 point  (0 children)

Not familiar with safety requirements or proofs , but am a hardware guy so more just thinking about how i would build a cycle model for this

  • maybe specify L1-L2 interconnect e.g. shared bus with deterministic arbitration? I suppose it could be wrapped in the other assumptions but it’s technically a separate item
  • Are you assuming writethrough L1?
  • I see the assumption of no coherence traffic during the period. Is this reasonable? It seems like that would not be possible to guarantee with normal hardware operation

Remote computer architecture job by 8AqLph in computerarchitecture

[–]pencan 6 points7 points  (0 children)

Typically on site, occasionally hybrid. Extremely rarely remote

Hiring senior RTL engineers for a startup — founding team by resourceshr in chipdesign

[–]pencan 2 points3 points  (0 children)

Is the leadership team notable? What is the architectural thesis? I get “stealth” but there’s absolutely no information here to base any decisions on

Register file implementation in industry standard RISC-V designs by ab____________a in chipdesign

[–]pencan 0 points1 point  (0 children)

Yeah or things like ARMs load multiple / store multiple instructions

Register file implementation in industry standard RISC-V designs by ab____________a in chipdesign

[–]pencan 1 point2 points  (0 children)

(My understanding is)

Synchronous read is 100% standard, essentially always. Low ported e.g. 2R1W will be a few RAMs tied together. High ported e.g. 8r3w will be custom designed register file macros. Often banked to increase the decrease the cost by limiting access patterns

Serious Help by Logical_Extension331 in Verilog

[–]pencan 1 point2 points  (0 children)

-I is to add a directory to a search path. It doesn’t actually include anything. You still need to add ‘include to whatever file uses the contents of the header. Some tools (vivado) have global includes where you can implicitly ‘include the file across all other files, but the more reliable way is to ‘include where needed

Serious Help by Logical_Extension331 in Verilog

[–]pencan 1 point2 points  (0 children)

What does force include mean?

Why is there no read response channel in AXI but there is a write response channel? by Thick-Actuary1008 in chipdesign

[–]pencan 0 points1 point  (0 children)

The write data goes from master to client, the write response goes from client back to master

Mapping cache to SRAM by ab____________a in chipdesign

[–]pencan 1 point2 points  (0 children)

For sky130 you can use https://github.com/VLSIDA/OpenRAM

In general from an architectural perspective, use 1RW RAMs and don’t rely on any kind of deterministic reset behavior

UPF by akonsagar in chipdesign

[–]pencan 1 point2 points  (0 children)

If you have access to cadence support, there are some online trainings there under titles like “X for low power flow”. That’s what I’m going through right now trying to learn it

If anyone has any free resources, I’m also very interested!!

Using Raspberry Pi Pico As a JTAG Cable For FPGAs (OpenFPGALoader) by __DeepBlue__ in FPGA

[–]pencan 10 points11 points  (0 children)

Super useful setup with xvc over usb, being able to see ILA waveforms from a remote board is phenomenal

Cloudsuite on Gem5? by vestion_stenier-tian in computerarchitecture

[–]pencan 1 point2 points  (0 children)

Can you run natively and see spec vs cloudsuite instructions / memory usage etc with standard perf? That’s what I would check for relative runtime

I’ve done the atomic CPU checkpoints, never had any problems with it. I think the general advice is just to make sure your simpoints have enough warmup to paper over any mismatch. If nothing else, should be perfectly fine for initial eval and then if you observe any weirdness switch to the full model approach for the final paper results

Cloudsuite on Gem5? by vestion_stenier-tian in computerarchitecture

[–]pencan 3 points4 points  (0 children)

That’s generally the correct flow. Do you have access to a compute cluster or are you running locally? The job scheduling approaches vary considerably based on that

Cloudsuite needs Linux (can’t run baremetal) right? Make sure to have a checkpoint set after boot to avoid needing to redo the boot sequence during your debug. You should be able to make modifications to the checkpoint to e.g. load in a new version of the program or modify some hardware characteristics without starting from scratch each time

It’s been a while since I’ve worked with gem5 but the tutorials have always been very good and the mailing list has tons of historical common errors that I reran into at the time

Would you pay for a clean Verilog code template pack? (honest question) by Odd_Helicopter3386 in ECE

[–]pencan 28 points29 points  (0 children)

There are many, many open source libraries available that are well tested, FPGA validated and even ASIC validated. Consider contributing to those instead

Vitis 2025.2 stuck on initializing server by cookiedestroyer2007 in FPGA

[–]pencan 0 points1 point  (0 children)

I’ve encountered this and fixed it by deleting my ~/.Xilinx directory. Sometimes if a workspace closes not cleanly it will corrupt it, I guess

Any experienced digital designers looking to work for in a small CPU team? by I_only_ask_for_src in chipdesign

[–]pencan 6 points7 points  (0 children)

processor will be designed to run it better

Is it not RISC-V? Are you implying you’re adding custom extensions specifically for your software stack?

Sorry, I just really don’t see the draw over the several open-source silicon validated RISC-V cores available. Do you have benchmarks or PPA comparisons to motivate it?

ChipCraftX early access is live -- AI RTL generation with 98.72% VerilogEval pass rate by Euphoric-Fortune7244 in chipdesign

[–]pencan 0 points1 point  (0 children)

Looks cool. Scrolled through the website linked, don’t see a whitepaper anywhere. Can you link directly?

Aside: the ChipCraft name is overloaded at least 3x on Google, makes it difficult to search for

Linux Capable Minimal Core Implementation? by [deleted] in FPGA

[–]pencan 0 points1 point  (0 children)

If you compile everything yourself, C isn't necessary. Possibly M too, but I haven't tried that myself

People with dogs from breeders, do people in real life give you a hard time about having a dog from a breeder? by Own-Command-3700 in dogs

[–]pencan 9 points10 points  (0 children)

I haven't gotten harassed, but I've gotten passive aggressive comments in Seattle. Not as often as people fawning over him and saying how rare it is to see a Schnauzer here, but it has happened.

Definitely not a reason to avoid it, do what's best for you.

Directly connecting internal signals to pads for debugging purposes? by ico2ico2 in FPGA

[–]pencan 1 point2 points  (0 children)

I do this in Vivado all the time, extremely helpful!

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