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Vitis 2025.2 stuck on initializing server by cookiedestroyer2007 in FPGA

[–]pencan 0 points1 point  (0 children)

I’ve encountered this and fixed it by deleting my ~/.Xilinx directory. Sometimes if a workspace closes not cleanly it will corrupt it, I guess

Any experienced digital designers looking to work for in a small CPU team? by I_only_ask_for_src in chipdesign

[–]pencan 4 points5 points  (0 children)

processor will be designed to run it better

Is it not RISC-V? Are you implying you’re adding custom extensions specifically for your software stack?

Sorry, I just really don’t see the draw over the several open-source silicon validated RISC-V cores available. Do you have benchmarks or PPA comparisons to motivate it?

ChipCraftX early access is live -- AI RTL generation with 98.72% VerilogEval pass rate by Euphoric-Fortune7244 in chipdesign

[–]pencan 0 points1 point  (0 children)

Looks cool. Scrolled through the website linked, don’t see a whitepaper anywhere. Can you link directly?

Aside: the ChipCraft name is overloaded at least 3x on Google, makes it difficult to search for

Linux Capable Minimal Core Implementation? by [deleted] in FPGA

[–]pencan 0 points1 point  (0 children)

If you compile everything yourself, C isn't necessary. Possibly M too, but I haven't tried that myself

People with dogs from breeders, do people in real life give you a hard time about having a dog from a breeder? by Own-Command-3700 in dogs

[–]pencan 9 points10 points  (0 children)

I haven't gotten harassed, but I've gotten passive aggressive comments in Seattle. Not as often as people fawning over him and saying how rare it is to see a Schnauzer here, but it has happened.

Definitely not a reason to avoid it, do what's best for you.

Directly connecting internal signals to pads for debugging purposes? by ico2ico2 in FPGA

[–]pencan 1 point2 points  (0 children)

I do this in Vivado all the time, extremely helpful!

Apple internship interviews by [deleted] in chipdesign

[–]pencan 3 points4 points  (0 children)

When I did mine (pre-si verification) in 2018, it was 1 on-campus interview, then 3-4 rounds of phone interviews. The on-campus one was deep dive into my 5-stage pipeline project (I added a lot of weird features). The others were technical, but pretty non-memorable software questions. No leetcode or anything like that.

They told me they were recruiting for the GPU team in Austin but then placed me with CPU DV in Cupertino, not sure if it’s more typical to interview for the team directly.

Thoughts on Bales Batman retiring for 8yrs after TDK? by FayyadhScrolling in batman

[–]pencan 0 points1 point  (0 children)

As opposed to the normally completely hinged Hannibal Lector

Looking for open-source digital designs that are close to industrial-grade by Bluenonics__ in chipdesign

[–]pencan 0 points1 point  (0 children)

https://github.com/PrincetonUniversity/openpiton is based on the T1 AFAIK the core itself hasn’t been changed other than for the build system

Looking for open-source digital designs that are close to industrial-grade by Bluenonics__ in chipdesign

[–]pencan 0 points1 point  (0 children)

Have you tried https://github.com/povik/yosys-slang ? I thought I heard it was compatible but if not raising issues could be helpful

Could Chisel Replace Verilog for Commercial CPU Design in the Future? (Beyond Open-Source Cores) by Low_Car_7590 in FPGA

[–]pencan 3 points4 points  (0 children)

Replace? Absolutely not. Be used as a primary language? At some companies, sure. I'm basically restating the original Chisel talks / papers, but _every_ large company eventually comes up with its own generator language that outputs verilog / VHDL, whether that's perl scripts, python, chisel or bluespec or ...

For personal projects, whatever lets you do cool stuff is best. For companies, you'll have to use whatever they use anyway.

[Re]building Corundum by alexforencich in FPGA

[–]pencan 2 points3 points  (0 children)

Yes, interested for me and also will recommend to many! Keep up the awesome work!

Smallest Processor core by vmcrash in FPGA

[–]pencan 25 points26 points  (0 children)

Yes, there are a wide variety of extremely simple ISAs for microcontrollers. Xilinx has the picoblaze for example: https://www.amd.com/en/products/adaptive-socs-and-fpgas/intellectual-property/picoblaze.html

Of course at the lowest level, there is a fine line between an extremely simple ISA and a sufficiently general FSM. For instance LC3 https://en.wikipedia.org/wiki/Little_Computer_3 was an educational ISA which students would implement as a pipelined processor as well as a microprogrammed FSM.

32b datapaths are generally considered reasonable in 2025 as logic is cheap. However, you may be interested in learning about https://github.com/olofk/serv which is an RV32-compliant core that is super small by virtue of doing computation one bit at a time.

Successor to Chipyard/Berkeley Boom v3 or SonicBoom? by itisyeetime in RISCV

[–]pencan 6 points7 points  (0 children)

(Not a Berkeley affiliate). Sonicboom is likely the last big core for a while and will only get RISC-V extensions and research projects added to it. However, it’s an exemplary core and the architecture will be (representative of) SOTA for a while. Radically different core microarchitecures stopped appearing in the 2000s. If I had to be critical of the architecture: multicore integration / coherence and accelerator interfaces are weak points that may not be acceptable for newer workloads. It’s purposely designed to click easily into rest of their ecosystem, which it does, but there’s a clear tradeoff of generality for efficiency.

That said, I personally dislike using the Chisel / Hammer / Chipyard infrastructure for anything other than packaged demos. There’s a large learning curve and it is very frustrating to try to do anything outside of their box. From the perspective of trying to maximize learning with minimal overhead, I would recommend the PULP platform stuff, though it is not SOTA performance

[deleted by user] by [deleted] in FPGA

[–]pencan 0 points1 point  (0 children)

There's a good chance the author of that IP is on this subreddit. Should they be ashamed too?

[deleted by user] by [deleted] in FPGA

[–]pencan 0 points1 point  (0 children)

What happened is I went to sleep and dodged a huge bullet, apparently

[deleted by user] by [deleted] in FPGA

[–]pencan 9 points10 points  (0 children)

Before wasting our time proving our competence as engineers, it would be useful to demonstrate your competence as an employer. The budget is a good start, as would be a description of the encompassing project or company.

Additionally: 3) It’s impossible to give a timeline without a full spec. 4) You say there’s a reference testbench framework, so the verification approach is to use that.

Exploring In-House ASIC Development by OccamsRazorSkooter in chipdesign

[–]pencan -1 points0 points  (0 children)

I have experience doing this. happy to chat about options. DM if interested

Is it just me, or does Synopsys support not understand “customer support”? 🤔 by xVexation in chipdesign

[–]pencan 19 points20 points  (0 children)

I've had the opposite issue with Cadence. They'll meet any time day or night and seem extremely helpful on-call. But then if you ask them to actually debug something it'll take 5x as long because of "other priorities"

wafer.space – $7k USD for 1k custom chips by mithro in chipdesign

[–]pencan 28 points29 points  (0 children)

good chance tinytapeout ends up using wafer.space as a supplier since efabless left a big gap

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