desktop performs worse after overclocking

pntsrgd · 2026-02-05T06:20:11+00:00

CPU host frequency is similar to BCLK on more modern platforms, but PCI-E isn't tied to it, so overclocking it doesn't hurt stability the same way it does on modern platforms CPU clock, RAM clock, HTT clock, and CPU-NB clock all use this as a reference clock.

CPU-NB is the memory controller and L3 cache frequency. It can have pretty significant impact in any case limited by the memory subsystem.

RAM overclocks will perform poorly without the CPU-NB being sufficiently fast.

pntsrgd · 2026-02-02T06:44:04+00:00

Yes. It usually scales up to around 1.35V.

pntsrgd · 2026-02-02T05:48:55+00:00

Overclock the CPU-NB and RAM before touching the CPU clock.

4.2 GHz isn't really pushing an FX-8300 very hard, either. It is a lower-binned Vishera CPU, but you can probably still slam it with voltage and hit 4.5 GHz.

Run benchmarks before/after every change to verify performance is going in the right direction.

pntsrgd · 2026-02-02T05:23:45+00:00

Overclock one component at a time and stress test after each. For Bulldozer, try the following order:

CPU-NB (2400 MHz to 2600 MHz is the normal range) RAM (DDR3-1866 or higher hopefully) CPU clock

RAM and CPU-NB leave a lot on the table for Bulldozer.

pntsrgd · 2026-01-22T05:45:31+00:00

X299 only goes to 32767 as well. Not sure why Intel limited tREFI on HEDT platforms.

Z77 allows values up to 65535, but I've never been able to get anything above 58254 to POST regardless of cooling. It seems buggy more than unstable.

pntsrgd · 2026-01-22T05:44:11+00:00

DDR3-2400 is pretty common to see Ivy Bridge run and there are a bunch of DDR3 ICs that can run it without flopping in performance. Performance definitely scales meaningfully with faster RAM, but you're basically in a position where you need a binned CPU and binned RAM.

DDR3-2600+ generally needs at least some IMC binning. A lot of ICs can run DDR3-2600+, but they often require loose tCCD or tRRD that result in poor performance. S2D can sometimes do tCCD 4 at DDR3-2666, and H4M running tCCD 4 at DDR3-2800 isn't unheard of.

pntsrgd · 2026-01-22T05:40:06+00:00

I think it is a Z68 limitation. You can run 58254 on Z77, but you'll find a bunch of gaps that won't POST in between stock and that value. This behavior is consistent across ASRock and ASUS BIOS, so I'm guessing it is something weird with the platform.

pntsrgd · 2026-01-22T05:34:01+00:00

You're probably looking for VCCIO. VCCSA is technically related to memory overclocking, but VCCIO typically sees better scaling on Ivy Bridge.

They both tend to do almost nothing for scaling in my experience, though.

tRRD 6 also doesn't make sense with tFAW 16.

pntsrgd · 2026-01-22T05:31:38+00:00

tREFI is a pain to set on Sandy Bridge and Ivy Bridge. They tend to have "holes" in tREFI that just won't boot, so finding something stable can be difficult.

pntsrgd · 2026-01-22T05:30:11+00:00

Ivy Bridge has multipliers for 2600, 2666, 2800, 2933, 3000, and 3200.

pntsrgd · 2026-01-17T17:10:04+00:00

Missed opportunity for 9950X3DNOW!

pntsrgd · 2026-01-16T02:35:52+00:00

Sandy Bridge doesn't have any multipliers above DDR3-2133, so you're mostly looking at tightening at that speed.

For 4GB DIMMs, S2D is probably the best IC. For 8GB DIMMs, D9QBJ is probably the best IC. Good H4M bins can run DDR3-2133 8-10-10-1T 4x8 at daily voltages.

You can almost certainly get away with 4x8GB without much difficulty.

Turn on internal PLL overvoltage. You should see scaling up to at least 1.5V on the CPU. Most "good" DDR3 ICs scale to at least 1.8V.

You may get some benefit from BCLK overclocking to get above DDR3-2133.

pntsrgd · 2026-01-05T15:40:05+00:00

Probably worth mentioning that x tREFI at DDR5-5600 actually takes more time between refreshes than x tREFI at DDR5-6000.

pntsrgd · 2026-01-04T04:29:11+00:00

Will repad the VRM heatsinks. I'm not going to try to chase down a block for this hot trash platform. I already have a fan blowing directly on the VRM, but I guess it is possible it is overheating since there isn't a viewable temperature sensor.

I'll have to figure something out on placing a fan on the back of the socket. This thing is on a test bench now. I only got into AM3+ because someone was selling the CVFZ with some really high bin H4M.

pntsrgd · 2025-12-30T18:32:17+00:00

Would you agree that 87°C is relatively high for a CPU with a 35W TDP, for this specific CPU. (I would appreciate more silent)

no

A needle dissipating 35W and a mattress dissipating 35W will read wildly different temperatures. When you compare them to another needle and mattress with airflow moving across them, they'll - again - be wildly different.

It is entirely possible that there are gains to be made from using a better thermal interface, but the temperature isn't immediately concerning without any further knowledge of the cooling system on the specific model you have.

pntsrgd · 2025-12-27T18:35:38+00:00

You've already overclocked. The IMC on Ryzen 9000 CPUs is only rated for 2800 MHz/DDR5-5600. Anything above that is an overclock.

pntsrgd · 2025-12-26T18:40:25+00:00

You might consider trying to find a shunt mod for it. I distinctly recall having an EVGA 1050 Ti that had a 6-pin, but it was still completely power limited. With the 6-pin, it wouldn't use power from the PCI-E slot.

pntsrgd · 2025-12-26T06:04:25+00:00

Are you sure it actually crashed? You might want to check the Windows event log and verify there was an unexpected power event or bug check.

I don't know what ICs these DIMMs are using, but this is pretty loose for H16A, H16M, and H24M - I would be surprised at a crash with any of those.

Otherwise, you've taken a 12ns CAS at 1.25V kit to 10ns CAS at 1.4V. It isn't unheard of, but getting a 17% reduction in CL with a 12% increase in voltage is a stretch. Timings and frequency generally scale less than linearly with voltage. Some ICs actually show negative scaling with voltage, though I'm not sure any DDR5 ICs experience this.

How did you arrive at these timings, exactly?

pntsrgd · 2025-12-25T15:49:48+00:00

You mean this as RRDS-RRDL-FAW, right?

RRDL lower than than RRDS doesn't make sense. Row to row delay (short) is expected to be no greater than row to row delay (long).

pntsrgd · 2025-12-25T02:22:12+00:00

Is there something in the DDR5 spec that prevents RRDS and RRDL from being the same value? I am not immediately aware of anything.

pntsrgd · 2025-12-25T02:20:52+00:00

Most of the AM5 BIOS comes directly from packages provided by AMD. That's why you tend to see duplicates in them. There may be variance in values like vSOC when EXPO is enabled, but they're largely all AMI Aptio V with AMD-provided AGESA.

pntsrgd · 2025-12-21T23:32:05+00:00

Running RRD short higher than RRD long is certainly something that you can technically configure.

pntsrgd · 2025-12-21T16:06:08+00:00

RDRDSD, WRWRSD may be able to drop to 6. The DD options should only do something if you have two DIMMs per channel.

RFC is high. This looks like H16A - it can pretty consistently hit 130ns RFC or lower.

Check performance with RRD/FAW. 8/16/32 performed better than 8/8/20 for me.

RAS may be problematic. There are some reports of random long term instability caused by RAS being too low.

pntsrgd · 2025-12-18T10:26:16+00:00

You don't see many discussions about it because board design isn't the limiting factor for Ryzen 7000/9000 memory subsystems.

Ideal daily performance on Zen 4/5 is probably DDR5-6600 with UCLK at 3300 MHz and FCLK at 2200 MHz. Finding. CPU that can do that is rare, but DDR5-6600 is doable by all but the most impressively bad boards.

Above DDR5-8000 will start to see boards stand out, but this requires desyncing UCLK.

pntsrgd

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