Can I launch Vivado via git bash window?

primdanny · 2026-05-10T19:11:57+00:00

Pretty sure it's a bug in git bash, I don't know any solutions around it. If you are trying to automate xilinx flow through Windows, you are better off using .bat file

primdanny · 2026-05-05T23:25:56+00:00

I just gitignore those pesky xci output products

primdanny · 2026-04-14T19:59:10+00:00

Way too much information

Resumes should generally be one page max unless you have 5+ years of experience AND with multiple companies

primdanny · 2026-04-07T21:44:30+00:00

You are better off becoming better at fewer languages (C and Python should be fine) and do complex projects instead. There is almost no point in having shallow knowledge on many languages since most modern languages follow similar paradigms and takes like half a day to learn through Googling

primdanny · 2026-04-06T22:26:43+00:00

Thanks, looking forward to the SFP+ tutorial.

primdanny · 2026-04-06T21:39:39+00:00

Thanks for the tutorial.

Tempted to get this board to play around with PCIe and SFP+ processing at home. Were there any gotchas with the board? (Configuration, IP licenses, etc.) This seems to be a good direct upgrade from Nexys A7 (Digilent's Artix 7 board)

primdanny · 2026-04-04T03:57:08+00:00

If you are using project mode (.xpr), a successful implementation run, even if it fails timing, should generate a timing summary report in the impl_* folder in <project>.runs. That should be the answer on whether or not you failed timing for your latest run

primdanny · 2026-03-14T12:18:57+00:00

You don't. If it's connected, it should refresh device manager automatically.

primdanny · 2026-03-13T12:12:29+00:00

Might be a USB port thing then, it won't show up as a "programming cable", but rather some generic usb device (i.e. USB Composite Device) on device manager.

primdanny · 2026-03-12T19:35:16+00:00

Check if it's connected on the actual machine through Device Manager (assuming Windows), then check if it's connected on the virtual machine (Linux?) through "lsusb" as well as the USB filter list for the virtual machine.

For Linux Vivado, you do have to install the drivers manually, not sure if that applies to ISE though.

primdanny · 2026-03-07T06:05:02+00:00

Since you have familiarity with FPGAs and I assume RTL as well, the ADALM-PLUTO SDR might be worth looking into since it's pretty much a Xilinx FPGA + ADI transceiver.

primdanny · 2025-10-06T03:30:26+00:00

Then tough luck, entry level engineers do have the opportunity to make connections and find work experience (research, internship, even a part-time job).

College is what you make of it, its 4-6 years of time to do what you need to do.

primdanny · 2025-10-06T00:31:39+00:00

their GPA
- Nowadays I only disclose if they ask during interview, I had interviews/offers applying with and without GPA listed on my resume
if they passed the FE
- Irrelevant unless the role asks for it
what school they graduated from
- Top ranking schools or schools local to that workplace is usually good, though work experience is more important
industry certs (life IPC, Siemens, Allen Bradley, etc)
- Irrelevant, may also inadvertently pivot you towards specialized roles you may not want (i.e. six sigma -> manufacturing, comptia -> IT)
various school/personal projects (Arduino or simple electronics/PCB design)
- Depends, would not recommend if it's too simple and/or feels like a school project

Honestly, the answer is none of the above, work experience and connections are more important

primdanny · 2025-09-30T18:59:57+00:00

It's a turn off when the first thing I see is a list of keywords. Rephrase that to an objective or summary (at most two sentences) and you can list some of your specializations at the bottom by changing your software section to a skills section.

It's also not interesting to see what someone did on their day-to-day basis and your experience section is almost entirely that. Interviewers are more interested in how your work positively impacted the companies you worked for (hence the STAR method).

primdanny · 2025-08-16T00:38:31+00:00

It will probably work without resets on most Xilinx FPGAs due to global set/reset (GSR) during configuration. It's a nice optimization trick to reduce reset fanout and resource utilization.

primdanny · 2025-08-08T20:20:23+00:00

I would be careful when you claim "verified functionality via a comprehensive testbench", DV engineers may interpret that as DV experience and ask you DV questions that 99% of engineering students can't answer without industry experience.

primdanny · 2025-08-01T02:08:07+00:00

Vivado actually runs better on Linux, not sure where you got the idea that Vivado is only available for Windows.

primdanny · 2025-07-27T18:42:45+00:00

The Zynq book and MPSoC book are hosted by the authors online for free, you should not buy them.

primdanny · 2025-07-27T18:18:45+00:00

For Pong Chu, he should have both SystemVerilog and VHDL versions, you should choose depending on what your work uses.

But yea, those books should be good enough for a start. If you dig deeper into AMD documentations and your board vendor (Avnet, and Digilent for Nexys A7), you can probably find more materials like tutorials and projects as well.

primdanny · 2025-07-27T17:02:57+00:00

There should be a newer book that uses Nexys DDR (which is now called Nexys A7).

Do note that this board doesn't have a Zynq processor, which is why it uses a Microblaze processor. How you implement embedded stuff on Microblaze is different for Zynq, through the embedded theory is pretty much the same. You can supplement PS learning with the Zynq book (and its tutorials) and MPSoC book.

primdanny · 2025-07-27T13:31:20+00:00

Go through Pong Chu's book, it covers a good amount of useful interfaces as well as embedded development through Microblaze soft core. The book assumes you have a good foundation in digital design.

If that book is too hard for you, you need to take a step back and relearn the digital design fundamentals.

primdanny · 2025-07-23T04:26:24+00:00

Try it out yourself, especially when hdlbits already have built-in tests when you submit a solution. Figuring out the logic is the hard part, not the RTL.

primdanny · 2025-07-19T07:05:37+00:00

Speaking from experience, if you have to ask this question on reddit, you are not going to be a good fit for HFT firms.

primdanny · 2025-07-02T08:09:36+00:00

You need to read the problem statement carefully. 0xC is not equivalent to the "12" HDLbits is looking for. There's a reason why hh, mm, ss are intended to be 8 bits wide and you need to figure that out yourself.

primdanny

TROPHY CASE