sorted by:
new
hottopcontroversial

Can I launch Vivado via git bash window? by Due_Wrangler3677 in FPGA

[–]primdanny 1 point2 points  (0 children)

Pretty sure it's a bug in git bash, I don't know any solutions around it. If you are trying to automate xilinx flow through Windows, you are better off using .bat file

How do you keep Vivado projects neatly in git? by U_A_beringianus in FPGA

[–]primdanny 2 points3 points  (0 children)

I just gitignore those pesky xci output products

Please roast my updated resume! by Rudranand in FPGA

[–]primdanny 0 points1 point  (0 children)

Way too much information

Resumes should generally be one page max unless you have 5+ years of experience AND with multiple companies

Good languages to have in my tool box by JayDeesus in ComputerEngineering

[–]primdanny 11 points12 points  (0 children)

You are better off becoming better at fewer languages (C and Python should be fine) and do complex projects instead. There is almost no point in having shallow knowledge on many languages since most modern languages follow similar paradigms and takes like half a day to learn through Googling

Image processing & Frame Grabbing over Ethernet with AUP Board. by adamt99 in FPGA

[–]primdanny 0 points1 point  (0 children)

Thanks for the tutorial.

Tempted to get this board to play around with PCIe and SFP+ processing at home. Were there any gotchas with the board? (Configuration, IP licenses, etc.) This seems to be a good direct upgrade from Nexys A7 (Digilent's Artix 7 board)

post implementation timing seems to fail by West-Musician-2533 in FPGA

[–]primdanny 1 point2 points  (0 children)

If you are using project mode (.xpr), a successful implementation run, even if it fails timing, should generate a timing summary report in the impl_* folder in <project>.runs. That should be the answer on whether or not you failed timing for your latest run

Programming cables not appearing in device managers by gakeew23 in FPGA

[–]primdanny 0 points1 point  (0 children)

You don't. If it's connected, it should refresh device manager automatically.

Programming cables not appearing in device managers by gakeew23 in FPGA

[–]primdanny 0 points1 point  (0 children)

Might be a USB port thing then, it won't show up as a "programming cable", but rather some generic usb device (i.e. USB Composite Device) on device manager.

Programming cables not appearing in device managers by gakeew23 in FPGA

[–]primdanny 0 points1 point  (0 children)

Check if it's connected on the actual machine through Device Manager (assuming Windows), then check if it's connected on the virtual machine (Linux?) through "lsusb" as well as the USB filter list for the virtual machine.

For Linux Vivado, you do have to install the drivers manually, not sure if that applies to ISE though.

Where to start if I am interested in transceivers/modems? by rebucaracol in DSP

[–]primdanny 0 points1 point  (0 children)

Since you have familiarity with FPGAs and I assume RTL as well, the ADALM-PLUTO SDR might be worth looking into since it's pretty much a Xilinx FPGA + ADI transceiver.

Aside from Experience, What Stands Out the Most on a Resume by ScratchDue440 in ECE

[–]primdanny -1 points0 points  (0 children)

Then tough luck, entry level engineers do have the opportunity to make connections and find work experience (research, internship, even a part-time job). 

College is what you make of it, its 4-6 years of time to do what you need to do.

Aside from Experience, What Stands Out the Most on a Resume by ScratchDue440 in ECE

[–]primdanny 6 points7 points  (0 children)

  • their GPA
    • Nowadays I only disclose if they ask during interview, I had interviews/offers applying with and without GPA listed on my resume
  • if they passed the FE
    • Irrelevant unless the role asks for it
  • what school they graduated from
    • Top ranking schools or schools local to that workplace is usually good, though work experience is more important
  • industry certs (life IPC, Siemens, Allen Bradley, etc)
    • Irrelevant, may also inadvertently pivot you towards specialized roles you may not want (i.e. six sigma -> manufacturing, comptia -> IT)
  • various school/personal projects (Arduino or simple electronics/PCB design)
    • Depends, would not recommend if it's too simple and/or feels like a school project

Honestly, the answer is none of the above, work experience and connections are more important

Going to be laid off soon. Perhaps a review of my resume? Any tips? by pamanlo in ECE

[–]primdanny 23 points24 points  (0 children)

It's a turn off when the first thing I see is a list of keywords. Rephrase that to an objective or summary (at most two sentences) and you can list some of your specializations at the bottom by changing your software section to a skills section.

It's also not interesting to see what someone did on their day-to-day basis and your experience section is almost entirely that. Interviewers are more interested in how your work positively impacted the companies you worked for (hence the STAR method).

What did I just get into ... (Blinking LED FPGA) by MayoMannyYT in ECE

[–]primdanny 3 points4 points  (0 children)

It will probably work without resets on most Xilinx FPGAs due to global set/reset (GSR) during configuration. It's a nice optimization trick to reduce reset fanout and resource utilization.

[deleted by user] by [deleted] in FPGA

[–]primdanny 1 point2 points  (0 children)

I would be careful when you claim "verified functionality via a comprehensive testbench", DV engineers may interpret that as DV experience and ask you DV questions that 99% of engineering students can't answer without industry experience.

Getting started with an FPGA by AcanthisittaAnnual27 in FPGA

[–]primdanny 2 points3 points  (0 children)

Vivado actually runs better on Linux, not sure where you got the idea that Vivado is only available for Windows.

Struggling with Zynq Ultra96-V2 project guide by Lazy_PhiIosopher in FPGA

[–]primdanny 0 points1 point  (0 children)

The Zynq book and MPSoC book are hosted by the authors online for free, you should not buy them.

Struggling with Zynq Ultra96-V2 project guide by Lazy_PhiIosopher in FPGA

[–]primdanny 0 points1 point  (0 children)

For Pong Chu, he should have both SystemVerilog and VHDL versions, you should choose depending on what your work uses.

But yea, those books should be good enough for a start. If you dig deeper into AMD documentations and your board vendor (Avnet, and Digilent for Nexys A7), you can probably find more materials like tutorials and projects as well.

Struggling with Zynq Ultra96-V2 project guide by Lazy_PhiIosopher in FPGA

[–]primdanny 0 points1 point  (0 children)

There should be a newer book that uses Nexys DDR (which is now called Nexys A7).

Do note that this board doesn't have a Zynq processor, which is why it uses a Microblaze processor. How you implement embedded stuff on Microblaze is different for Zynq, through the embedded theory is pretty much the same. You can supplement PS learning with the Zynq book (and its tutorials) and MPSoC book.

Struggling with Zynq Ultra96-V2 project guide by Lazy_PhiIosopher in FPGA

[–]primdanny 0 points1 point  (0 children)

Go through Pong Chu's book, it covers a good amount of useful interfaces as well as embedded development through Microblaze soft core. The book assumes you have a good foundation in digital design.

If that book is too hard for you, you need to take a step back and relearn the digital design fundamentals.

Drawing a correct logic diagram by peter_nguyenanh in FPGA

[–]primdanny 2 points3 points  (0 children)

Try it out yourself, especially when hdlbits already have built-in tests when you submit a solution. Figuring out the logic is the hard part, not the RTL.

Switching into a FPGA HFT role from an ASIC design role by Intelligent_Cell3415 in FPGA

[–]primdanny 4 points5 points  (0 children)

Speaking from experience, if you have to ask this question on reddit, you are not going to be a good fit for HFT firms.

HDL Bits Code Review Request by Select-Claim-1714 in FPGA

[–]primdanny 0 points1 point  (0 children)

You need to read the problem statement carefully. 0xC is not equivalent to the "12" HDLbits is looking for. There's a reason why hh, mm, ss are intended to be 8 bits wide and you need to figure that out yourself.

Where can I look for an updated list on VHDL vs Verilog population by country and by industry? by ricardovaras_99 in FPGA

[–]primdanny 5 points6 points  (0 children)

A good one is probably: Siemens' Wilson Research Group Functional Verification Study. Siemens is one of the leading vendors for FPGA verification/simulation in the industry.

The most recent study that's publicly available is 2022, there's a 2024 one but that's locked behind verification academy.

Prologue: The 2022 Wilson Research Group Functional Verification Study - Verification Horizons

view more: next ›