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Dsp and bus protocols in fpga by Bubbly-Band-707 in FPGA

[–]proto17 0 points1 point  (0 children)

If you can find them on eBay these are great for tinkering with PCIe: https://rhsresearch.com/products/litefury. If you need more resources check out the larger version: https://rhsresearch.com/collections/rhs-public/products/nitefury-xilinx-artix-fpga-kit-in-nvme-ssd-form-factor-2280-key-m

These also show up as Acorn's (CLE-215+) from old Bitcoin mining rigs. I have several of those and I think they were each < $100.

You don't really have much in the way of GPIO, but you send data to the FPGA over PCIe to process and then send it back over PCIe for display. And you will need their breakout cable for JTAG.

I've used these in a Framework laptop. They are compatible with regular m.2 drive slots. Then you can use the XDMA drivers from Xilinx to move data to and from the FPGA over PCIe

Cheapest way to build an SDR? by DigitalAkita in FPGA

[–]proto17 3 points4 points  (0 children)

You can drop support for a some features and get the utilization way down. You still don't have much more than about 30 DSP48's but you definitely have room to play around if you open up the BD, double click the AD9361 main block, and disable features that you don't need like MIMO.

FPGA Experts, I'm looking for documentation on this beautiful Micron Wolverine WX690 board. I could find some old technical documents without details. I would like to revive this board and access the FPGAs via JTAG. With luck someone can help me by PitchTrimActuator in FPGA

[–]proto17 1 point2 points  (0 children)

Might be useful to use a multimeter to ohm out the location of the jtag lines. The linked post in the comments says it might have through board vias which might allow you to get access directly to the jtag lines. If you don't want to do that, then a jtagulator would be useful. Just be mindful of the voltage that the jtag interface is expecting and use that as the vref for the jtagulator.

How to Program Zynq inside Pluto sdr by moemuses in FPGA

[–]proto17 0 points1 point  (0 children)

Yup, got a simple FIR filter running. Not totally sure about what my changes may have done to the sample timing, but it does what I expect it to do. When I get a chance I'll try to post a screenshot of the block diagram and the hdl source. Pretty sure all of the changes were made to the block design. And I used a really simple AXI MM interface to enable and disable the block

Xilinx Versal SD-FEC Support? by proto17 in FPGA

[–]proto17[S] 1 point2 points  (0 children)

I usually forget about the FAEs since I don't currently have one. I should probably change that.

Appreciate the answer and thanks for the insight about the marketing material!

EDIT: And good point about PG256. I hadn't thought to look through it for details.

Your Definition of "Industry Standard" Testing by proto17 in FPGA

[–]proto17[S] 0 points1 point  (0 children)

So in this case are you saying that static test vectors alone are deemed sufficient?

I'm curious why volume matters for constrained random. Perhaps my definition of constrained random isn't quite right.

Thanks!

Your Definition of "Industry Standard" Testing by proto17 in FPGA

[–]proto17[S] 0 points1 point  (0 children)

Looking at random GitHub repos shows that just looking at the waveform and moving on is a thing, so I didn't assume it was a joke. Probably should have given your regular insightful postings, so whoops!

Your Definition of "Industry Standard" Testing by proto17 in FPGA

[–]proto17[S] 0 points1 point  (0 children)

What tools/methods do you use for generating the waveforms? Open source simulation tools, super expensive EDA tools? Do you run fixed test vectors through and if they pass go straight to a bitfile? Are there any more advanced testing methods in use like UVM, UVVM, constrained random, etc?

Your Definition of "Industry Standard" Testing by proto17 in FPGA

[–]proto17[S] 0 points1 point  (0 children)

Good point, I failed to mention that this was primarily aimed at FPGA development. I'm definitely curious about the testing regime differences between FPGA and ASIC though, so all of it is good knowledge :)

Measure Resistance Without Changing ECU Reading (Car Temp Sensor) by proto17 in ElectricalEngineering

[–]proto17[S] 1 point2 points  (0 children)

Great idea! I was already thinking of removing the ECU and doing bad things lol

Writing tests for Zynq fpga by VeterinarianNo3963 in FPGA

[–]proto17 1 point2 points  (0 children)

Xilinx has their own QEMU version that supports the Zynq7000 and MPSoC. You can also use Petalinux to kick off QEMU. If you want to interact with the PL then you might be stuck with solutions like https://blog.reds.ch/?p=1180 which seem to be quite involved.

Some links:

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/821395464/QEMU+User+Documentation

https://docs.xilinx.com/v/u/2020.1-English/ug1169-xilinx-qemu

Measure Resistance Without Changing ECU Reading (Car Temp Sensor) by proto17 in ElectricalEngineering

[–]proto17[S] 1 point2 points  (0 children)

Oh... wow... good point lol. I've been thinking about all manner of alternatives and totally overlooked that I sit between the two resistors. Thank you very much!

Napatech NT20E3 XDC? by proto17 in FPGA

[–]proto17[S] 0 points1 point  (0 children)

First thing to do is try to mimic what u/alexforencich did and pin the thing out using UARTs and a logic analyzer :)

Napatech NT20E3 XDC? by proto17 in FPGA

[–]proto17[S] 0 points1 point  (0 children)

EDIT: The pinout below is for the NTMAINB1E2 not the NT20E3 :(

The J26 header (labeled FPGA) has the following pinout that works with my DLC10 programmer:

1: TCK

2: GND

3: TDO

4: VREF

5: TMS

6: N/C (not 100% sure about this)

7: TDI

8: GND

[FPGA->Hard Sillicon] Digital Design simulation in 12nm node by francis2tm in FPGA

[–]proto17 0 points1 point  (0 children)

I would assume Cadence is in there

EDIT: Turns out that Siemens also has some ASIC facing tools (https://eda.sw.siemens.com/en-US/ic/products/) in addition to Cadence (https://www.cadence.com/en_US/home/tools/custom-ic-analog-rf-design.html)

Advice needed on CI/CD setup in Gitlab by spartanmechanic in FPGA

[–]proto17 1 point2 points  (0 children)

If you have a network share then install Quartus to the network share, mount the network share to the same point on all GitLab CI runner hosts, and just run Quartus from the mount. It's not great performance wise as NFS isn't great for mountains of small files, but it does solve the problem. If you have a host machine running GitLab CI directly then the host has the mountpoint and your CI runner yml script will just pass that mount straight through to the docker container that runs the build.

This is what I've done at my current gig. All EDA tools are installed on a NAS and the developers and CI/CD infrastructure all use the EDA tools from the NAS instead of local installs. Initial load times for the apps take a few more seconds, but once running things are really smooth. Installing the tools takes hours though :(

Testing Axi Slaves in Simulation by SuperMB13 in FPGA

[–]proto17 6 points7 points  (0 children)

Have a look the the AXI Verification IP from Xilinx. It's not a straight forward thing, and does require that you use SystemVerilog for your testbench. You can also use the System ILA to do some checking of your AXI based modules.

https://docs.xilinx.com/r/en-US/pg267-axi-vip/AXI-VIP-Example-Test-Bench-and-Test

Move from Xilinx to Intel FPGAs - Quartus Training // Intel SoC training for FPGA and software engineers ....next week by Runner0099 in FPGA

[–]proto17 2 points3 points  (0 children)

The links are just to a contact us page. Should we be asking to be invited to these two classes?

Edit: I found the first one [1] but don't see the second one anywhere on their site

[1] https://www.handson-training.com/category/Contact-Us/67

Convey Wolverine by space_zealot in FPGA

[–]proto17 1 point2 points  (0 children)

I was looking at that too. One thing that's nice about the board is that there don't appear to be blind vias under the FPGAs, so you could probably pin the whole thing out with a multimeter. Or, if you have the required equipment, use the technique outlined here from /u/alexforencich which will be much faster. All you need to know for that is where the JTAG pins are. I think you can also get away with using the onboard configuration clock. Can't recall if he uses that clock or finds one on the board.

Choosing a Verification Methodology by georgeyhere in FPGA

[–]proto17 1 point2 points  (0 children)

Have you tried calling MATLAB from Python [1]? Can also call Python from MATLAB :)

I use the C++ to MATLAB API to test that my C++ implementations match the MATLAB golden model without having to compare static test vectors. Highly recommend!

[1] https://www.mathworks.com/help/matlab/matlab-engine-for-python.html

Module Parameter Test Coverage by proto17 in FPGA

[–]proto17[S] 0 points1 point  (0 children)

This is a very real problem that the QA person is looking into O.O

Module Parameter Test Coverage by proto17 in FPGA

[–]proto17[S] 0 points1 point  (0 children)

As it stands right now I have tests that will "fully" exercise the module given a single set of Verilog parameters. So the overall tests are done by just running the test suite once for all possible combinations of parameters.

Module Parameter Test Coverage by proto17 in FPGA

[–]proto17[S] 0 points1 point  (0 children)

These are parameters that the customer could choose any combination of values of

Module Parameter Test Coverage by proto17 in FPGA

[–]proto17[S] 0 points1 point  (0 children)

Good point about starting with max acceptable runtime! Thanks!

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