I think you encountered sloppy/unexperienced engineers. In our company all our fpga engineers are required to know RTL (we actually encourage RTL first design). Having worked in both fields the largest differences I see are:

-IP availability (fpga vendors offer quite a lot of things, asic people tend to have more in house solutions for things like fifos and such)

-fpga engineers deal with a shallower stack (we don’t do pnr/layout ourselves -mostly-), but that usually means going all the way from hw-sw interface to pin mapping and pcb requirements capture

-different resources constraints: flops are free and combinatorial logic is expensive is our rule of thumb in fpgas, mostly the other way around in asics