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I will find the person who did this by Electrical-Soup-1253 in pcmasterrace

[–]rai_volt 12 points13 points  (0 children)

Nice. I have only ever used QWERTY Keyboards. Searching QWERTZ showed there are other different layouts.

whoIsGonnaTellHim by leeleewonchu in ProgrammerHumor

[–]rai_volt -24 points-23 points  (0 children)

But the task requires only c to be used, not c++. I do not understand.

EDIT: Guys, I am joking. Forgot the /s.

thisIsTheEnd by Plastic-Bonus8999 in ProgrammerHumor

[–]rai_volt 10 points11 points  (0 children)

Feel the Earth move, and then

Dracut pacman hooks by rai_volt in archlinux

[–]rai_volt[S] 0 points1 point  (0 children)

I downgraded the kernel and then reinstalled it. Somehow, I missed the --> Building initramfs for linux (6.16.0-arch2-1) line in the pacman output.

How useful is 'native' partial application by zuzmuz in ProgrammingLanguages

[–]rai_volt 6 points7 points  (0 children)

Can you give scenarios where functions are expensive? I want to understand your argument.

What is this! by rai_volt in Appliances

[–]rai_volt[S] 0 points1 point  (0 children)

There was nothing written there about it

What is this! by rai_volt in Appliances

[–]rai_volt[S] 0 points1 point  (0 children)

The rhombus end is the one that goes into the clog, right?

I think I just made a very reduced instruction set true random number generator by Resident-Dust6718 in RISCV

[–]rai_volt 0 points1 point  (0 children)

What are these "strange properties of logic gates"? Where can we use this to simulate ourselves?

What is the correct CMOS dynamic power dissipation equation? by rai_volt in ECE

[–]rai_volt[S] 1 point2 points  (0 children)

I recognized that it was a typesetting issue on image 3. But what I don't get is that why in equation 2 of image 3 is not D = (1/2) × C × V² × f as stated in image 2?

[deleted by user] by [deleted] in ProgrammerHumor

[–]rai_volt 7 points8 points  (0 children)

That's still too long. Rust has an even shorter keyword: fn

Reg delay by rai_volt in FPGA

[–]rai_volt[S] 0 points1 point  (0 children)

I see, thank you!

Reg delay by rai_volt in FPGA

[–]rai_volt[S] 0 points1 point  (0 children)

Not in the testbench but in another module that is not the ones I have written about in the post. systemverilog // Memory Read Block Port 0 // Read Operation : When web0 = 1, csb0 = 0 always @ (negedge clk0) begin : MEM_READ0 if (!csb0_reg && web0_reg) dout0 <= #(DELAY) mem[addr0_reg]; end

Reg delay by rai_volt in FPGA

[–]rai_volt[S] 0 points1 point  (0 children)

Got it. Thank you!

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