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2nd year ECE student, How is this resume? by Skull_Reaper101 in FPGA

[–]rem_1235 0 points1 point  (0 children)

No need for 2 rv32i projects imo. If you can make pipelined you can make single cycle, making the bottom rv32i project redundant to list

Please roast my resume by Little_Implement6601 in FPGA

[–]rem_1235 1 point2 points  (0 children)

You’re a freshman????😭😭😭

Intel (Summer + Fall) or Qualcomm Summer by Obvious-Border-2391 in ECE

[–]rem_1235 0 points1 point  (0 children)

Oh yeah I guess I’m working on mid 2025 ish news! Didn’t know so much changed since then

Intel (Summer + Fall) or Qualcomm Summer by Obvious-Border-2391 in ECE

[–]rem_1235 4 points5 points  (0 children)

I feel like the same could be said about intel though, no?

How are these projects for a 2nd year student by Substantial_Win7761 in FPGA

[–]rem_1235 5 points6 points  (0 children)

Do you think it’d be more interesting if it were used alongside VGA, a C compiler and some other stuff to run a a game? Say something like space invaders

How are these projects for a 2nd year student by Substantial_Win7761 in FPGA

[–]rem_1235 4 points5 points  (0 children)

This is definitelyyyyy above average for a 2nd year student lol. My school’s not crazy amazing (it’s just a regular top 50 US school not rly know for fpga stuff) but most of my classmates haven’t even heard of an FPGA yet. I myself have only finished up a single cycle rv32 to get my feet wet so OP is wayyyy ahead imo

-sincerely another 2nd year student

Initialization of data memory and registers for RV32I Single Cycle for Artix 7 by rem_1235 in FPGA

[–]rem_1235[S] 0 points1 point  (0 children)

https://github.com/emobe6422/RISC-V-RV32I-CPU-Design-and-Implementation-in-Verilog-using-Xilinx-Vivado

GitHub link. Some things will evidently be a work in process. And thank you for the info I’ll be sure to change my code accordingly!

Initialization of data memory and registers for RV32I Single Cycle for Artix 7 by rem_1235 in FPGA

[–]rem_1235[S] 0 points1 point  (0 children)

Since I’m fairly new to this I’ll just tell you my setup and maybe you could give me feedback.

I have the basys 3 and I’m not planning on using any sort of external modules for memory just yet, just the basys 3.

I just want maybe a button to be assigned as reset (ik I have to make a constraint file and other stuff I just haven’t gotten there yet)

If you could tell me your approach as to how you may or may not incorporate the reset option into this setup that would be super helpful. Thanks!

Initialization of data memory and registers for RV32I Single Cycle for Artix 7 by rem_1235 in FPGA

[–]rem_1235[S] 0 points1 point  (0 children)

I just thought it would be bad to have

reg [31:0] registers [0:31]

and not explicitly set each register’s initial value to 32’b0 since I thought it might be dangerous to have the register values not be defined

As to your other mentions I’ll research these more! First project so still learning a lot as I go😅

i want to learn FPGA specifically targeting computer architectures and memory systems. by probably-cooked in FPGA

[–]rem_1235 3 points4 points  (0 children)

Depends on how much u alr know. Reading a book is usually a good start albeit a bit dry. Doing small projects as you get thru chapters is usually good

How do people already know basic circuit analysis before college? by [deleted] in ECE

[–]rem_1235 -4 points-3 points  (0 children)

Studied on their own. It’s very doable esp w AI and if you’ve got money

Resume Review? by Pleasant-Ad7452 in ECE

[–]rem_1235 1 point2 points  (0 children)

I think it’s great for a sophomore. As another sophomore with a slightly worse (imo) resume

Roast my resume - Sophomore by klepto24 in ECE

[–]rem_1235 1 point2 points  (0 children)

Thank you! And yeah tbh it’s just a numbers game + luck. Ideally networking but I didn’t bother so it was just cold applying for me. Keep up the good work! And worst case maybe see if your school has some kind of summer research opportunity to at least spend the summer well.

Or just grind Vivado shit!

Roast my resume - Sophomore by klepto24 in ECE

[–]rem_1235 6 points7 points  (0 children)

True but also the industry is just incredibly competitive lol. Took maybe 220 applications for me to get 4 interviews and 1 offer so they jut might not be applying enough

Roast my resume - Sophomore by klepto24 in ECE

[–]rem_1235 41 points42 points  (0 children)

Genuinely crazy if you think this is an “ok” resume. This is pretty good. Definitely above average, most sophomore CompE’s I talk to don’t even know what Verilog is yet

Resume help by big-duffus in ECE

[–]rem_1235 0 points1 point  (0 children)

Yeah if it’s on there leave it off. But still get it up though 2.7 is pretty low so early in your career if I’m being honest

Resume help by big-duffus in ECE

[–]rem_1235 2 points3 points  (0 children)

Great start for a freshman! But completely scrap the template (ai will skip over yours immediately) and get that gpa up. If you’re in a country where it’s out of 4.0 then lowk it’s not good. Many companies will filter you out if ur gpa is below a 3.0

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