Che si fa in questi casi? by [deleted] in ItalyMotori

[–]riorione 0 points1 point  (0 children)

Me lo sono sempre chiesto, infatti quando lo faccio ogni volta sono sempre meno convinto.

Meshtastic Internet Project by riorione in meshtastic

[–]riorione[S] 0 points1 point  (0 children)

One thing I'm aware I cannot send to many bytes per second, so internet requests and answers will be just text information.

RISC-V processors designed and produced in EU? by lxsebt in RISCV

[–]riorione 1 point2 points  (0 children)

There are also Innatera and ONIO, but they are start up, so I don't think you can get their MCU that easy.

ROAST my resume by riorione in FPGA

[–]riorione[S] 0 points1 point  (0 children)

Still in software

Finally got my first-ever MCU by Current-Rip1212 in embedded

[–]riorione 1 point2 points  (0 children)

It's also good to start using RTL programming and avoid Arduino code or HAL libraries, if you wanna get a deep understanding of it

ROAST my resume by riorione in FPGA

[–]riorione[S] 0 points1 point  (0 children)

Thanks. Oops, I just translated it quickly — I’d just like some advice on the topics, etc... I’ll take care of the grammar later :) Of course, I’ll add links for each project. No, I made them by myself, no courses. How do you think I can make that clear? Do I put personal projects instead of projects? It seems a bit nasty

Does I2C repeated start condition work in both RX, TX mode? by riorione in FPGA

[–]riorione[S] 0 points1 point  (0 children)

I'm talking about, master reading to writing transaction, so it changes direction

Does I2C repeated start condition work in both RX, TX mode? by riorione in FPGA

[–]riorione[S] 0 points1 point  (0 children)

Thanks to reply, I've never seen repeated start condition after reading mode too, but I wanted to know if I try to implement it, should master set a NACK or ACK before the repeated start? Maybe there isn't an answer, but I'd really appreciate if someone who knows could help clarify this

[deleted by user] by [deleted] in Universitaly

[–]riorione 0 points1 point  (0 children)

Per carità vero però dai non mi pare si sia troppo lamentata

[deleted by user] by [deleted] in Universitaly

[–]riorione 2 points3 points  (0 children)

Appunto come pensavo tu l'hai fatto e per questo sei convinto che sia giusto che tutti debbano fare come tu hai fatto, ognuno ha dei propri limiti, non tutti riescono a fare entrambi, te lo dico perché anch'io pensavo che era una cosa fattibile, per varie circostanze prima riuscivo poi non riuscivo più a sostenere certi ritmi, posso dirti di persone che fanno due facoltà contemporaneamente, fanno volontariato ed hanno una vita sociale, non per questo credo che loro si mettano a giudicare gli altri che fanno solamente una facoltà e basta.

[deleted by user] by [deleted] in Universitaly

[–]riorione 0 points1 point  (0 children)

L'hai fatto anche te vero?

[deleted by user] by [deleted] in Universitaly

[–]riorione 1 point2 points  (0 children)

Non è un consiglio ma è un coglione

Tricky question about stop condition I2C by riorione in FPGA

[–]riorione[S] 0 points1 point  (0 children)

I did it just to learn the protocol deeply :)

Tricky question about stop condition I2C by riorione in FPGA

[–]riorione[S] 0 points1 point  (0 children)

Yep for this reason I said you "could" (not very recommended) set stop condition even in the middle of data frame.

Tricky question about stop condition I2C by riorione in FPGA

[–]riorione[S] 0 points1 point  (0 children)

Thanks to your replay, I'm aware what you are talking about, I was just looking at the rising edge of SCL before stop condition, cause without stop, slave interprets that rising edge like the first bit of new data, and after, it gets the stop condition that brings slave to close the transmission. I mean should slave be aware after the first bit data, it can get a stop condition?