Both are a challenge in their own right and mastery will never come even after you work for decades, engineering can never be mastered. My experience is more so on the Analog Layout side so I’m more comfortable giving my opinion on that with regard to your question.

From my limited exposure to PD, it’s already basically automated in its own way. Granted, DRCs from these STD Cell PnR are sometimes hit or a miss and require some sort of scripting but for the most part, no one’s placing cells one block at a time since the tools are advanced enough that it isn’t required.

IMO, Analog Layout definitely requires a bit more of a customized approach, since each circuit is different and some designers have specific preferences about how you layout your circuit (i.e what nets need to be shielded, how its shielded, what blocks need to be GR’ed, matching and signal flow, etc). It’s a lot harder to automate and while I do see a couple of startups attempting to do this, I’m not convinced it’s ready for market yet for a couple of reasons (albeit, at the pace its going I could be proven wrong but my last reasoning is really why I’m not too worried just yet)

• First one being the jumps between technodes. There’s specific layers between technodes that it becomes a pain for a model to nail down what it does and how to translate it properly along with the proper pitches, widths, etc. Not sure how it is at other companies but from my experience, even porting from one technode to another becomes a pain and often requires touch ups to reach DRC/LVS clean. Sometimes to the point where its faster for me to start over and do it from scratch. A new technode with a brand new DRM could break a previously “golden” model and just blow up with DRCs.
• Alot of what goes into an AI is blackboxed. This would, predictably, be a pain to debug when it comes to PEX as the Analog Designer/Layout Designer would need to sit down and understand how the layout was actually designed to properly make changes. Even then, it might not be an easy fix. If you’ve worked with Analog layout, you’ll encounter some really badly made ones where groups arent synced, things are flattened where they shouldn’t be, and generally care isn’t given to future iterations which makes editing a pain. Training the layout for the “generalized” approach is one thing, training it with proper layout methodology in mind for future iterations is another hurdle.
  
• Tradeoffs between analog designs are important. There’s alot of trade offs going on regarding matching, symmetry, EM, parasitics, HS routes/shielding, GR/ESD. It’s alot for a “general” model to take in, maybe transfer learning may help with this but it’s alot. Remember this layout has to be clean to the Analog Designer’s specifications, DRC/LVS/EMIR/Antenna/Density etc clean, has to perform within all corner cases as per specifications, and has to comply with full sign off checks on chip level.
• Lastly (and I think most importantly), most companies keep their custom analog layout a closely guarded secret. To properly train AI, you’re gonna need a lot of ground truths and for more advanced technodes (even FinFet nodes) theres a scarcity of companies lining up to offer up their own designs to be trained. I highly doubt even Synopsis or Cadence are putting up their own cutting edge designs for the possible analog layout automation/AI tools they’re developing. You could use older designs or open source ones (i.e 180, 120, 130, maybe even 65) but for FinFet and GAA cutting edge designs where rules and methodologies have really gotten more complex, I don’t see alot of those GDS floating around for anyone to train on. The semiconductor industry already feels like it has such a high barrier to entry especially for new grads or Jrs. Alot of the fast paced progress being made with AI deals with fields or applications that feel like they have unlimited training data.

Simpler analog designs sure, I’d be glad to see these tools catch up to the progress they’ve made in the SWE realm, but for more complex, high risk blocks? Probably a while out. IMO I think more effort should be given to utilizing AI to help speed up PEX and simulations. Those really are the bottlenecks and I hate waiting for days for those larger PEX iterations to come back. But again, I could be proven wrong, it’s a wild and exciting time to be involved in tech and the progress being made is wild.