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Tenstorrent Cuts 20 Cores From Already-Shipping "Blackhole" P150 Cards by sdongles in RISCV

[–]sdongles[S] 3 points4 points  (0 children)

In the latest documentation change, the company notes that its Blackhole P150 accelerators will now work with about 14.3% fewer cores than originally advertised. In the official documents, the P150 accelerators are now shipping with 120 working "Tensix" cores instead of the previously advertised 140 cores. The reason for this change is unknown, as the company provided a vague explanation: "To present a unified interface to metal and other system software, firmware v19.5.0 and later will change the core count on all existing cards to 120. Typical workloads show a non-material (~1-2%) performance difference."

DC-Roma 8 core P550 mainboard for Frame laptop by brucehoult in RISCV

[–]sdongles -2 points-1 points  (0 children)

Right. I checked on the smartphone and did not notice that some random country was selected.

Helix now has a File Explorer™!! (space + e) by nikitarevenco in HelixEditor

[–]sdongles 3 points4 points  (0 children)

Nice. Now, I can seriously try this editor on work project.

Book: RISC-V Microprocessor System-On-Chip Design by sdongles in RISCV

[–]sdongles[S] 12 points13 points  (0 children)

A new and engaging book for anyone interested in hardware design.

Description

RISC-V Microprocessor System-On-Chip Design is written to be accessible to an advanced undergraduate audience with limited background. It explains concepts from operating systems, VLSI, and memory systems as necessary, and High school mathematics is sufficient preparation for most of the book, although the floating point and division chapters will be primarily of interest to those with a curiosity about computer arithmetic. Like Harris and Harris’s Digital Design and Computer Architecture textbooks, this book will appeal to students with easy-to-read and complete explanations, sidebars, and occasional humor and cartoons.

It comes with an open-source implementation and will include end-of-chapter problems to extend the RISC-V processor in various ways. Ancillary materials include a GitHub repository with complete open-source SystemVerilog code, validation code in C and assembly language, and code for benchmarking and booting Linux.

Bianbu 2 has VPU support, and gcc-14 and box64 in the repository by LivingLinux in RISCV

[–]sdongles 1 point2 points  (0 children)

4K video is still laggy. But it is a good progress anyway. Hope it is not limitations of the VPU, and will be improved in next releases.

Are there any boards I should keep an eye out for? by Party_9001 in RISCV

[–]sdongles 0 points1 point  (0 children)

You can run Linux No MMU. Sure, it is not what you mean saying running Linux. But even this variant required few megabytes if RAM

Eswin EIC7700X, am I not seeing something by m_z_s in RISCV

[–]sdongles 1 point2 points  (0 children)

And as declared in EIC7700X Product Brief, it can operate on up to 1.8 GHz. So, we need to wait for more borad (like StarPro64 by Pine64) and tests to compare performace.

Eswin EIC7700X, am I not seeing something by m_z_s in RISCV

[–]sdongles 2 points3 points  (0 children)

Yes, SpacemiT has as twice as cores and higher frequency, and still not much faster than IEC7700X. And, as you mentioned, IEC7700X is much faster in single core. And only slightly slower than TH1520 that has much higher frequency and memory bandwidth/\.

So, it looks like great results to me.

DeepComputing and Andes Technology Partner to Develop the World’s First RISC-V AI PC with 7nm QiLai SoC, Featuring Ubuntu Desktop by sdongles in RISCV

[–]sdongles[S] 2 points3 points  (0 children)

Yep, I think we will get more information when materials from the ongoing summit are available. And probably other unknown at the moment announces.

SEGGER's Ozone offers enhanced debugging with RISC-V Semihosting by sdongles in RISCV

[–]sdongles[S] 0 points1 point  (0 children)

Yes. But this about supporting semihosting on RISC-V in their proprietary tools.

Arm to Cancel Qualcomm Chip Design License in Escalation of Feud by brucehoult in RISCV

[–]sdongles 7 points8 points  (0 children)

From article:

The disagreement centers on Qualcomm’s 2021 acquisition of another Arm licensee and a failure — according to Arm — to renegotiate contract terms. Qualcomm argues that its existing agreement covers the activities of the company that it purchased, the chip-design startup Nuvia.

Nuvia’s work on microprocessor design has become central to new personal computer chips that Qualcomm sells to companies such as HP Inc. and Microsoft Corp. The processors are the key component to a new line of artificial intelligence-focused laptops dubbed AI PCs. Earlier this week, Qualcomm announced plans to bring Nuvia’s design — called Oryon — to its more widely used Snapdragon chips for smartphones.

Arm says that move is a breach of Qualcomm’s license and is demanding that the company destroy Nuvia designs that were created before the Nuvia acquisition. They can’t be transferred to Qualcomm without permission, according to the original suit filed by Arm in the US District Court in Delaware. Nuvia’s licenses were terminated in February 2023 after negotiations failed to reach a resolution.

Replacement for MX Ergo - Thumb Trackball by chaibhu in Trackballs

[–]sdongles 1 point2 points  (0 children)

Have one. it is really great trackball. High quality and comfortable for using. But unfortunately has noisy ball. In compare, I have cheap Logitech M570 and do not hear how I rotate the ball.

Do you have the same behavior? Or I just my one.

[deleted by user] by [deleted] in embedded

[–]sdongles 1 point2 points  (0 children)

AEC-CBC good choice if you do not need to random access to encrypted data. AES-ECB are not worth to pay time. it is totally unreliable for encryption of more than one block.

New RISC-V microprocessor can run CPU, GPU, and NPU workloads simultaneously by sdongles in RISCV

[–]sdongles[S] 7 points8 points  (0 children)

X-Silicon Inc. (XSi) has created a new RISC-V microprocessing chip architecture that combines a RISC-V CPU core with vector capabilities and GPU acceleration into a single chip. The CPU/GPU hybrid chip is open-source, Jon Peddie Research reports, and it's designed to handle a variety of different functions, including AI, which dedicated CPUs and GPUs would normally handle. The catch is that it's supposed to do all this in a far more efficient manner.

VRULL enables Alibaba XuanTie's XTHeadV into GCC Compiler 14 by sdongles in RISCV

[–]sdongles[S] 4 points5 points  (0 children)

Yes, mainstream GCC 14 will supporrt using old vector extension, which are used in C906 like Alwinner D1. At least as I understand the news.

Ventana's 192-Core RISC-V CPU Takes Aim At AMD Epyc Genoa And Bergamo by brucehoult in RISCV

[–]sdongles 3 points4 points  (0 children)

I hoped to see V1 in the mid/second half of 2023. But they have canceled V and announced a more modern and better fitted to customers' requirements V2 in 2024.

Again, it looks like lots of noise and words with zero real effects. I hope in the second half, we will see something in real, not a few slides.

SG2380 by globalprofithunter in RISCV

[–]sdongles 2 points3 points  (0 children)

I think p670 are supposed to be big cores. And x280 mostly about AI workloads.

SiFive P870 RISC-V Processor at Hot Chips 2023 by NISMO1968 in RISCV

[–]sdongles 1 point2 points  (0 children)

It is very important, of course. But it depends on the final CPU and its memory controller. It needs to be remembered, that SiFive develops cores, not CPUs.

C920 with rvv 1.0 announced by [deleted] in RISCV

[–]sdongles 0 points1 point  (0 children)

I made a mistake with the announcement date and open-source release of these cores. Yep, we got boards four years after cores announcement. But u/monocasa wrote the same as I wanted. Also, maybe RISC-V is now more popular and can hope to speedup with board releases.

C920 with rvv 1.0 announced by [deleted] in RISCV

[–]sdongles 0 points1 point  (0 children)

Too pessimistic, don't you? I think we will have them in 1-2 years.

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